
Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
21
4 Hardware Architecture
(continued)
4.2 DSP16000 Core Architectural Overview
(continued)
4.2.5 Core Block Diagram
DSP16000 Core Block Diagram
Figure 2. DSP16000 Core Block Diagram
ptrap(20)
DAU
+
XAAU
SINGLE
–1, 0, 1
MUX
+
YAAU
MUX
COMPARE
SYS
cstate (16)
csave (32)
CACHE
CONTROL
(32)
IVALUE
OFF-
SHIFT(0, –1)
16
×
16 MULTIPLY
16
×
16 MULTIPLY
SPLIT/MUX
SAT.
ALU/ACS
ADDER/ACS
BMU
MUX
MUX
MUX/EXTRACT
ENCODER
SHIFT(0, –1)
SHIFT(0, –1)
SWAP MUX
(SHIFT
SAT.
SHIFT(0, –15, –16)
SAT.
SAT.
SHIFT(2, 1, 0, –2)/SAT.
KEY:
PROGRAM-ACCESSIBLE REGISTERS
MODE-CONTROLLED OPTIONS
PSG
BUSES
SAT.
SAT.
SAT.
ar3 (16)
ar0 (16)
ar1 (16)
ar2 (16)
c0 (16)
c1 (16)
c2 (16)
vsw (16)
y (32)
x (32)
p0 (32)
p1 (32)
a0 (40)
a7 (40)
a2 (40)
a3 (40)
a4 (40)
a5 (40)
a6 (40)
inc1 (20)
cloop (16)
PC (20)
vbase (20)
pr (20)
(20)
(20)
XDB
(32)
IDB
(32)
YAB
(20)
YAB
(20)
re1 (20)
rb1 (20)
sp (20)
k (20)
j (20)
DOUBLE
–2, 0, 2
31 INSTRUCTIONS
alf (16)
(32)
XDB
IDB
(32)
SINGLE
–1, 0, 1
MUX
IMMEDIATE
VALUE
i (20)
h (20)
DOUBLE
–2, 0, 2
Associated with
PC
-relative branch addressing.
Associated with register-plus-displacement indirect addressing.
XAB
(20)
YAB
(20)
TO
MEMORY
FROM
MEMORY
TO/FROM
MEMORY
TO
MEMORY
(32)
IDB
(32)
TO
PERIPH-
ERAL
XDB
YDB
XAB
XAB
M
re0 (20)
rb0 (20)
r0 (20)
r1 (20)
r2 (20)
r3 (20)
r4 (20)
r5 (20)
r6 (20)
r7 (20)
auc0 (16)
auc1 (16)
psw0 (16)
psw1 (16)
a1 (40)
SHIFT(2, 1, 0, –2)/SAT.
ins (20)
inc0 (20)
pt0 (20)
pt1 (20)
pi (20)
M
DEMUX