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參數(shù)資料
| 型號(hào)： | DSP16410C |
| 英文描述： | TVS 400W 7.0V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 151/373頁(yè) |
| 文件大小： | 5643K |
| 代理商： | DSP16410C |
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Data Sheet
June 2001
DSP16410B Digital Signal Processor
Agere Systems Inc.
Agere Systems—Proprietary
Use pursuant to Company instructions
95
4 Hardware Architecture
(continued)
4.13 Direct Memory Access Unit
(DMAU)
(continued)
4.13.9 Programming Examples
(continued)
4.13.9.1 SWT Example 1: A Two-Dimensional
Array
(continued)
The user software running in CORE0 must perform the
following steps to properly initialize SWT0:
1. The user software sets the source address
(
SADD0
—
Table 37 on page 76
) and the source
base address (
SBAS0
—
Table 44 on page 80
) to the
top of the output (source) array located in
TPRAM0. The user software writes 0x00002000 to
SADD0
and 0x02000 to
SBAS0
.
2. The user software sets the destination address
(
DADD0
—
Table 37 on page 76
) and the destination
base address (
DBAS0
—
Table 45 on page 80
) to the
top of the input (destination) array located in
TPRAM0. The user software writes 0x00001000 to
DADD0
and 0x01000 to
DBAS0
.
3. The user software clears the source and destination
counter registers
SCNT0
and
DCNT0
(
Table 38 on
page 77
and
Table 40 on page 78
).
4. The user software initializes the limit register
(
LIM0
—
Table 42 on page 79
) with the dimensions of
the array. The number of rows (or elements) is 2r
(
320), so the user software writes 319 (2r – 1) into
the LASTROW[12:0] field (
LIM0
[19:7]). The number
of columns is 4, so the user software writes 3 (n – 1)
into the LASTCOL[6:0] field (
LIM0
[6:0]). The user
software writes 0x09F83 into
LIM0
.
5. The user software initializes the stride register
(
STR0
—
Table 46 on page 81
) with the distance
between corresponding rows of consecutive col-
umns. Because the buffers are contiguous in this
example, the stride is the same as the buffer length
and the user software writes 0x0140 into
STR0
.
6. The user software initializes the reindex register
(
RI0
—
Table 47 on page 81
) with the sign-magnitude
postmodification value to be applied to
SADD0
and
DADD0
after each time that the last column has
been accessed. The magnitude of the reindex value
is ((2r
×
(n – 1)) – 1) or (320
×
3) – 1 = 959 = 0x3BF.
The sign must be negative, so the user software
writes 0x803BF into
RI0
.
7. The user software writes the control registers to
enable SWT0 and begin I/O processing. First, the
user software writes one into the POSTMOD[1:0]
field (
CTL0
[5:4]—
Table 34 on page 73
) to enable
two-dimensional array accesses, writes 0x3 to the
SIGCON[2:0] field (
CTL0
[3:1]), and writes 1 to the
AUTOLOAD field (
CTL0
[0]) so that no further core
interaction is needed. The user software writes
0x0017 to
CTL0
.
8. Finally, the user software sets both the SRUN0 and
DRUN0 fields (
DMCON0
[0] and
DMCON0
[4]—
Table 31 on page 70
) to enable SWT0 source and
destination transfers. The user software writes
0x0011 to
DMCON0
.
The DMAU begins processing the SWT0 input and out-
put channels. For the output channel, the DMAU per-
forms the following steps:
1. It reads the single word at the TPRAM0 location
pointed to by
SADD0
(0x00002000) and transfers
the data to SIU0. This data is the first output sample
for the first logical channel (ROW = 0 and COL = 0).
2. It increments
SADD0
by the contents of
STR0
, so
SADD0
contains 0x00002140 and points to the first
output sample for the second logical channel
(ROW = 0 and COL = 1). It updates
SCNT0
by
incrementing the column counter, so
SCNT0
con-
tains 0x00001.
3. It reads the data at 0x02140 and transfers it to SIU0.
4. It increments
SADD0
by the contents of
STR0
, so
SADD0
contains 0x00002280 and points to the first
output sample for the third logical channel (ROW = 0
and COL = 2). It updates
SCNT0
by incrementing
the column counter, so
SCNT0
contains 0x00002.
5. As in steps 3 and 4, the DMAU continues to read
data, transfer the data to SIU0, and update
SADD0
and
SCNT0
until the column counter equals the last
column (
SCNT0
[6:0] =
LIM0
[6:0] = 3).
SADD0
con-
tains 0x000023C0 and points to the first row of the
last column.
6. The DMAU subtracts the magnitude of the contents
of
RI0
from
SADD0
(0x000023C0 – 0x3BF) and
places the result into
SADD0
(0x00002001).
SADD0
points to the second output sample for the
first logical channel (ROW = 1 and COL = 0).
The DMAU continues processing in this manner until it
processes row 159 of column 3. At this point,
ROW = LASTROW/2 and COL = LASTCOL. Because
this condition is met and SIGCON[2:0] = 0x3, the
DMAU asserts the DSINT0 interrupt to CORE0.
CORE0’s ISR changes SIGCON[2:0]
to
0x5 so that the
DMAU asserts DSINT0 again after it has processed the
remaining samples in the buffers. CORE0 can over-
write the already-processed samples while the DMAU
continues to process the remaining samples.
The steps performed by the DMAU for the input chan-
nel are similar to those for the output channel.
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