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參數(shù)資料
| 型號： | DS4550E+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 9B 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 接口： | I²C，JTAG |
| 輸入/輸出數(shù)： | 9 |
| 中斷輸出： | 無 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 包括： | EEPROM |
DS4550
Test Access Port (TAP)
Controller State Machine
The TAP controller is a finite state machine that
responds to the logic level at TMS on the rising edge of
TCK (see Figure 4).
Test-Logic-Reset. Upon power-up, the TAP controller
is in the Test-Logic-Reset state. The Instruction
Register contains the IDCODE instruction. All system
logic of the device operates normally.
Run-Test/Idle. The Run-Test/Idle state is used between
scan operations or during specific tests. The Instruction
Register and test data registers remain idle.
Select-DR-Scan. All test data registers retain their previ-
ous state. With TMS LOW, a rising edge of TCK moves
the controller into the Capture-DR state and initiates a
scan sequence. TMS HIGH during a rising edge on TCK
moves the controller to the Select-IR-Scan state.
Capture-DR. Data can be parallel-loaded into the test
data registers selected by the current instruction. If the
instruction does not call for a parallel load or the select-
ed test data register does not allow parallel loads, the
test data register remains at its current value. On the
rising edge of TCK, the controller goes to the Shift-DR
state if TMS is LOW or it goes to the Exit1-DR state if
TMS is HIGH.
Shift-DR. The test data register selected by the current
instruction is connected between TDI and TDO and
shifts data one stage toward its serial output on each
rising edge of TCK while TMS is LOW. On the rising
edge of TCK, the controller goes to the Exit1-DR state if
TMS is HIGH.
Exit1-DR. While in this state, a rising edge on TCK
puts the controller in the Update-DR state. A rising
edge on TCK with TMS LOW puts the controller in the
Pause-DR state.
Pause-DR. Shifting of the test data registers is halted
while in this state. All test data registers retain their pre-
vious state. The controller remains in this state while
TMS is LOW. A rising edge on TCK with TMS HIGH
puts the controller in the Exit2-DR state.
Exit2-DR. A rising edge on TCK with TMS HIGH while in
this state puts the controller in the Update-DR state. A ris-
ing edge on TCK with TMS LOW enters the Shift-DR state.
I2C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
10
____________________________________________________________________
Figure 4. TAP Controller State Diagram
TEST-LOGIC-RESET
1
11
0
RUN-TEST/IDLE
0
1
0
1
0
1
0
1
0
1
SELECT-DR-SCAN
SELECT-IR-SCAN
CAPTURE-DR
CAPTURE-IR
SHIFT-DR
SHIFT-IR
EXIT1-DR
EXIT1-IR
PAUSE-DR
PAUSE-IR
EXIT2-DR
EXIT2-IR
UPDATE-DR
UPDATE-IR
0
1
0
1
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