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參數(shù)資料
| 型號： | DS4550E+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 9B 20TSSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 接口： | I²C，JTAG |
| 輸入/輸出數(shù)： | 9 |
| 中斷輸出： | 無 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 包括： | EEPROM |
DS4550
I2C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
4
_____________________________________________________________________
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Writes
+70°C (Note 3)
50,000
Note 1: All voltages referenced to ground.
Note 2: ISTBY is specified with SDA = SCL = TMS = TDI = VCC, outputs floating, and inputs connected to VCC or GND.
Note 3: Guaranteed by design.
Note 4: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing.
Note 5: After this period, the first clock pulse is generated.
Note 6: CBtotal capacitance of one bus line in picofarads.
Note 7: EEPROM write time applies to all the EEPROM memory and SRAM-shadowed EEPROM memory when SEE = 0. The
EEPROM write time begins after a stop condition occurs.
Note 8: TCK can be stopped either high or low.
Note 9: EEPROM write begins immediately after the UPDATE-DR state that latches the data to be written. The EEPROM cannot be
accessed until the EEPROM write has completed. However, the remainder of the JTAG functionality is active and accessi-
ble during the EEPROM write.
TCK
t1
t2
t3
t4
t5
t6
t7
TDI, TMS
TDO
Figure 1. JTAG Timing Diagram
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