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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DS4550E+T&R |
| 寤犲晢锛� | Maxim Integrated Products |
| 鏂囦欢闋佹暩(sh霉)锛� | 17/18闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC I/O EXPANDER I2C 9B 20TSSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 妯欐簴鍖呰锛� | 2,500 |
| 鎺ュ彛锛� | I²C锛孞TAG |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 9 |
| 涓柗杓稿嚭锛� | 鐒� |
| 闋荤巼 - 鏅傞悩锛� | 400kHz |
| 闆绘簮闆诲锛� | 2.7 V ~ 5.5 V |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 20-TSSOP锛�0.173"锛�4.40mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 20-TSSOP |
| 鍖呰锛� | 甯跺嵎 (TR) |
| 鍖呮嫭锛� | EEPROM |
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Memory Map and Memory Types
The DS4550 memory map is shown in Table 1. Three
different types of memory are present in the DS4550:
EEPROM, SRAM-shadowed EEPROM, and SRAM.
Memory locations specified as EEPROM are NV.
Writing to these locations results in an EEPROM write
cycle for a time specified by tWR in the AC Electrical
Characteristics table. Locations specified as SRAM-
shadowed EEPROM can be configured to operate in
one of two modes specified by the SEE bit (the LSB of
the Configuration Register, F4h). When the SEE bit = 0
(default), the memory location acts like EEPROM.
However, when SEE = 1, shadow SRAM is written to
instead of the EEPROM. This eliminates both the EEP-
ROM write time, tWR, as well as the concern of wearing
out the EEPROM. This is ideal for applications that wish
to constantly write to the I/Os. Power-up default states
can be programmed for the I/Os in EEPROM (with SEE
= 0) and then once powered up, SEE can be written to
a 1 so that the I/Os can be updated periodically in
SRAM. The final type of memory present in the DS4550
is standard SRAM.
DS4550
I2C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
8
_____________________________________________________________________
ADDRESS
TYPE
NAME
FUNCTION
FACTORY
DEFAULT
00h to 3Fh
EEPROM
User Memory
64 Bytes of General-Purpose User EEPROM.
00h
40 to E7h
Reserved
Undefined Address Space for Future Expansion. Reads and writes to
this space will have no affect on the device.
E8 to EFh
EEPROM
Reserved
F0h
Pullup Enable
0
Pullup Enable for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the
MSB. Set the corresponding bit to enable the pullup; clear the bit to
disable the pullup.
00h
F1h
Pullup Enable
1
Pullup Enable for I/O_8. I/O_8 is the LSB. Only the LSB is used. Set
the LSB bit to enable the pullup on I/O_8; clear the LSB to disable the
pullup.
00h
F2h
I/O Control 0
I/O Control for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB.
Clearing the corresponding bit of the register pulls the selected I/O
pin low; setting the bit places the pulldown transistor into a high-
impedance state. When the pulldown is high impedance, the output
will float if no pullup/down is connected to the pin.
FFh
F3h
I/O Control 1
I/O Control for I/O_8. I/O_8 is the LSB. Only the LSB is used. Clearing
the LSB of the register pulls the I/O_8 pin low; setting the LSB will
place the pulldown transistor into a high-impedance state. When the
pulldown is high impedance, the output will float if no pullup/down is
connected to the pin.
01h
F4h
Configuration
Configuration Register. The LSB is the SEE bit. When set, this bit
disables writes to the EEPROM; writing only effects the shadow
SRAM. When set to 0, both the EEPROM and the shadow SRAM is
written
00h
F5h to F7h
SRAM
Shadowed
EEPROM
[EEPROM
writes are
disabled if
the SEE bit
= 1]
User Memory
3 bytes of General-Purpose User EEPROM
00h
F8h
I/O Status 0
I/O Status for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB.
Writing to this register has no effect. Read this register to determine
the state of the I/O_0 to I/O_7 pins.
F9h
I/O Status 1
I/O Status for I/O_8. I/O_8 is the LSB. Only the LSB is used; the other
bits could be any value when read. Writing to this register has no
effect. Read this register to determine the state of the I/O_8 pin.
FAh to FFh
SRAM
SRAM User
Memory
6 Bytes of General-Purpose SRAM
Table 1. DS4550 Memory Map
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MAX7318AAG+ | IC I/O EXPANDER I2C 16B 24SSOP |
| MAX7312AUG+ | IC I/O EXPANDER I2C 16B 24TSSOP |
| MAX7319ATE+T | IC I/O EXPANDER I2C 8B 16TQFN-EP |
| MAX7322AEE+T | IC I/O EXPANDER I2C 4B 16QSOP |
| MAX7321AEE+T | IC I/O EXPANDER I2C 8B 16QSOP |
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鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| DS456 | 鍒堕€犲晢:Miyama Electric 鍔熻兘鎻忚堪: |
| DS4560 | 鍒堕€犲晢:MAXIM 鍒堕€犲晢鍏ㄧū:Maxim Integrated Products 鍔熻兘鎻忚堪:12V Hot-Plug Switch |
| DS4560LS-AR+ | 鍔熻兘鎻忚堪:鐔辨彃鎷斿姛鐜囧垎甯� RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Controllers & Switches 闆绘祦闄愬埗: 闆绘簮闆诲-鏈€澶�:7 V 闆绘簮闆诲-鏈€灏�:- 0.3 V 宸ヤ綔婧害鑼冨湇: 鍔熺巼鑰楁暎: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Tube |
| DS4560LS-AR+T | 鍔熻兘鎻忚堪:鐔辨彃鎷斿姛鐜囧垎甯� RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Controllers & Switches 闆绘祦闄愬埗: 闆绘簮闆诲-鏈€澶�:7 V 闆绘簮闆诲-鏈€灏�:- 0.3 V 宸ヤ綔婧害鑼冨湇: 鍔熺巼鑰楁暎: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Tube |
| DS4560LS-LO+ | 鍔熻兘鎻忚堪:鐔辨彃鎷斿姛鐜囧垎甯� RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Controllers & Switches 闆绘祦闄愬埗: 闆绘簮闆诲-鏈€澶�:7 V 闆绘簮闆诲-鏈€灏�:- 0.3 V 宸ヤ綔婧害鑼冨湇: 鍔熺巼鑰楁暎: 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MSOP-8 灏佽:Tube |
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