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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� DS3183N
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 62/400闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC TRPL ATM/PACKET PHY 400-PBGA
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
椤�(l猫i)鍨嬶細 瑾�(di脿o)骞€鍣�
鎳�(y墨ng)鐢細 鏁�(sh霉)鎿�(j霉)鍌宠几
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
灏佽/澶栨锛� 400-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 400-PBGA锛�27x27锛�
鍖呰锛� 绠′欢
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DS3181/DS3182/DS3183/DS3184
154
Error insertion can be initiated by a register bit (PLCP.TEIR.TSEI) or initiated by the manual error insertion input
(TMEI). Each error type is individually enabled by a register bit. The error insertion initiation type (register or input)
is programmable. Once all error insertion has been performed, the data stream is passed on to overhead insertion.
10.8.5.4 Transmit DS3 PLCP Overhead Insertion
Overhead insertion can insert any (or all) of the path overhead bytes into the DS3 PLCP frame. The overhead
bytes Z6 鈥� Z1, F1, B1, G1, M1, M2, and C1 can be sourced from the transmit overhead interface (TPOHCLK,
TPOH, TPOHEN, and TPOHSOF). The B1 and C1 bytes are sourced as error masks (modulo 2 addition of the
input B1/C1 byte and the generated B1/C1 byte). The overhead insertion is fully controlled by the transmit
overhead interface. If the transmit PLCP overhead data enable signal (TPOHEN) is driven high, then the bit on the
transmit PLCP overhead signal (TPOH) is inserted into the output data stream. Insertion of bits using the TPOH
signal overwrites internal overhead insertion.
10.8.6 Receive DS3 PLCP Frame Processor
The DS3 PLCP frame format is shown in Figure 10-32. A1 and A2 are the sub-frame Alignment bytes that have a
value of F6h and 28h respectively. P11 鈥� P0 are the Path Overhead Identifier (POI) bytes that indicate the path
overhead byte contained in the current sub-frame. Z6 鈥� Z1 are growth bytes reserved for future use. F1 is the Path
User Channel byte allocated for user communications purposes (This byte is undefined in ATM). B1 is the Bit
Interleaved Parity-8 (BIP-8) byte used for PLCP path error monitoring. G1 is the PLCP Path Status Byte (See
Figure 10-33) used for far-end path status and performance monitoring (bits 6 鈥� 8 are undefined in ATM). M1 and
M2 are the DQDB Layer Management Information bytes used for DQDB layer management communications
(These bytes are undefined in ATM). C1 is the Cycle/Stuff Counter byte used as for PLCP superframe alignment
and stuff indication.
10.8.6.1 Receive DS3 PLCP Framing
DS3 PLCP framing determines the DS3 PLCP frame boundary. The frame boundary is found by identifying the
frame alignment bytes (A1 & A2), and the path overhead indicator (POI) byte (P#). The framer is an off-line framer
that updates the data path frame counters when an out of frame (OOF) condition is present. The use of an off-line
framer reduces the number of ATM cells discarded during the framing process. The framer continually searches for
two consecutive sets of alignment bytes (A1 and A2), and two sequential POI bytes (P#) are identified. The data
path frame counters are updated if an OOF condition is present. The maximum average reframe time is 17
s.
10.8.6.2 Receive DS3 PLCP Nibble Destuffing
Nibble destuffing discards the DS3 PLCP frame trailer immediately following sub-frame 0 (POI equals 01h). The
trailer size is determined by the DS3 PLCP superframe counter, and the cycle counter byte (C1). The trailer is 13
nibbles in the first frame of the superframe (C1 equals FFh). The trailer is 14 nibbles in the second frame of the
superframe (C1 equals 00h). The trailer length is variable in the third frame of the superframe. It is 14 nibbles if C1
equals 66h and 14 nibbles if C1 equals 99h. The superframe counter is updated immediately upon receiving an
error free C1. In the third superframe, majority voting (5 of 8) is used to determine the trailer size. Once the trailer
size has been determined, the trailer nibbles are discarded.
10.8.6.3 Receive DS3 PLCP Performance Monitoring
Performance monitoring checks the DS3 PLCP frame for errors and alarm conditions. The alarm conditions
detected are OOF, LOF, COFA, and RAI. All alarm conditions are defect conditions. The PLCP Framer does not
integrate alarms for failure conditions.
An Out Of Frame (OOF) condition is declared when two consecutive framing bytes (A1 and A2) or two consecutive
POI bytes (P0 - P11) are erred. An OOF condition is terminated when two sequential POI bytes and two
consecutive framing words (A1 and A2) are error free or the DS3 PLCP framer updates the data path frame
counters.
If the Loss Of Frame (LOF) integration counter is disabled, an LOF condition is declared when an OOF condition
has been continuously present for 1 ms. If the LOF integration counter is enabled, an LOF condition is declared by
the LOF integration counter when the counter has been active for a total of 1 ms. The LOF integration counter is
active (increments count) when an OOF condition is present, it is inactive (holds count) when an OOF condition is
absent, and it is reset when an OOF condition is continuously absent for 1 ms. An LOF condition is terminated
when an OOF condition is continuously absent for 1 ms.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ESM44DSAI CONN EDGECARD 88POS R/A .156 SLD
FMC15DRYS-S93 CONN EDGECARD 30POS .100 DIP SLD
HCC49DRAI-S734 CONN EDGECARD 98POS .100 R/A PCB
LFX200EB-03F256I IC FPGA 200K GATES 256-BGA
LFX200EB-03FN256I IC FPGA 210KGATES 256FPBGA
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鍙冩暩(sh霉)鎻忚堪
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DS3184N 鍔熻兘鎻忚堪:缍�(w菐ng)绲�(lu貌)鎺у埗鍣ㄨ垏铏曠悊鍣� IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray
DS3184N+ 鍔熻兘鎻忚堪:缍�(w菐ng)绲�(lu貌)鎺у埗鍣ㄨ垏铏曠悊鍣� IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray
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*鍨嬭櫉(h脿o) *鏁�(sh霉)閲� 寤犲晢 鎵硅櫉(h脿o) 灏佽
娣诲姞鏇村閲囪臣(g貌u)

鎴戠殑鑱�(li谩n)绯绘柟寮�

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