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DS3181/DS3182/DS3183/DS3184
93
FF.RCR.RFRST = 1.
Clear the FIFO Reset bits.
FF.TCR.TFRST = 0.
FF.RCR.RFRST = 0.
Set the FIFO Transmit Level Control Register and the FIFO Transmit Port Address Control Register.
Set the FIFO Receive Level Control Register and the FIFO Receive Port Address Control Register.
The Port Address needs to be configured to match the master controller address for each port.
STEP 10: Configure the System Bus
Configure for bus size and for interface type. See Table 9-1.
Optionally, set the System Interface Transmit Control Register, System Interface Receive Control Register
#1 and #2 to fine tune for the specific application.
(User may leave registers at default value.)
STEP 11: Configure the Cell or Packet Processor
For cell mode, the default is to send the cell across the system interface without the HEC. Also, default
mode scrambles the cell data to the line.
To attach the HEC to the cell, set SI.TCR.THECT = 1 and SI.RCR.RHECT = 1.
STEP 12: Enable each port (for non-LIU modes)
PORT.CR2.TLEN = 1
Table 9-1. Configuration of Global Register Settings
Note: This table assumes a DS3 clock input on the CLKA pin.
MODE
0x002
4
0x00A
UTOPIA L2
0000 XX00 0000 0000
0x0204
0x0000
UTOPIA L3
0000 XX01 0000 0000
0x0204
0x0000
POS-PHY L2
0000 XX10 0000 0000
0x0204
0x0000
POS-PHY L3 or SPI-3
0000 XX11 0000 0000
0x0204
0x0000
8-Bit System Bus
0000 00XX 0000 0000
0x0204
0x0000
16-Bit System Bus
0000 01XX 0000 0000
0x0204
0x0000
32-Bit System Bus
0000 10XX 0000 0000
0x0204
0x0000
Table 9-2. Configuration of Port Register Settings
Note: The Line Mode has been configured with the LIU enabled and the JA in the receive path (LM[2:0] = 011) for all modes except OHM mode.
Only Port 1 registers have been displayed.
MODE
0x040
0x042
0x044
0x046
DS3 C-Bit
0x7C00
0000 0011 0000 000X
0x0000
DS3 C-Bit PLCP
0x7C00
0000 0011 0000 010X
0x0000
DS3 M23
0x7C00
0000 0011 0000 100X
0x0000
DS3 M23 PLCP
0x7C00
0000 0011 0000 110X
0x0000
E3.751
0x7C00
0000 0011 0001 000X
0x0000
E3.751 PLCP
0x7C00
0000 0011 0001 010X
0x0000
E3.823
0x7C00
0000 0011 0001 100X
0x0000
OHM Mode (DS3/E3/Clear
Channel)
0x7C00
1100 0XXX 00XX XXXX
0x0000
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