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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� DS3183N
寤犲晢锛� Maxim Integrated Products
鏂囦欢闋佹暩(sh霉)锛� 19/400闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC TRPL ATM/PACKET PHY 400-PBGA
鐢�(ch菐n)鍝佸煿瑷撴ā濉婏細 Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
妯欐簴鍖呰锛� 1
椤炲瀷锛� 瑾�(di脿o)骞€鍣�
鎳夌敤锛� 鏁�(sh霉)鎿�(j霉)鍌宠几
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 400-BBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 400-PBGA锛�27x27锛�
鍖呰锛� 绠′欢
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DS3181/DS3182/DS3183/DS3184
115
Figure 10-8. Performance Monitor Update Logic
GL.SR.GPMS
PORT.SR.PMS
PORT.CR1.PMU
PORT.CR1.PMUM
1
0
00
01
1X
GL.CR1.GPM
GL.CR1.GPMU
GPIO8(GPMU) PIN
ONE SEC
PERF
COUNTER
other port counters
other ports
PMU PMS
GTZ
10.4.6 Transmit Manual Error Insertion
Transmit errors can be inserted in some of the functional blocks. These errors can be inserted using register bits in
the functional blocks, using the global GL.CR1.TMEI bit, using the port PORT.CR1.TMEI bit, or by using the GPIO6
pin configured for TMEI mode.
There is a transmit error insertion register in the functional blocks that allow error insertion. The MEIMS bit controls
whether the error is inserted using the bits in the error insertion register or using error insertion signals external to
that block. When bit MEIMS=0, errors are inserted using other bits in the transmit error insertion register. When bit
MEIMS=1, errors are inserted using a signal generated in the port or global control registers or using the external
GPIO6 pin configured for TMEI operation.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ESM44DSAI CONN EDGECARD 88POS R/A .156 SLD
FMC15DRYS-S93 CONN EDGECARD 30POS .100 DIP SLD
HCC49DRAI-S734 CONN EDGECARD 98POS .100 R/A PCB
LFX200EB-03F256I IC FPGA 200K GATES 256-BGA
LFX200EB-03FN256I IC FPGA 210KGATES 256FPBGA
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鍙冩暩(sh霉)鎻忚堪
DS3184 鍔熻兘鎻忚堪:缍�(w菐ng)绲℃帶鍒跺櫒鑸囪檿鐞嗗櫒 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray
DS3184+ 鍔熻兘鎻忚堪:缍�(w菐ng)绲℃帶鍒跺櫒鑸囪檿鐞嗗櫒 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray
DS3184DK 鍔熻兘鎻忚堪:缍�(w菐ng)绲¢枊鐧�(f膩)宸ュ叿 RoHS:鍚� 鍒堕€犲晢:Rabbit Semiconductor 鐢�(ch菐n)鍝�:Development Kits 椤炲瀷:Ethernet to Wi-Fi Bridges 宸ュ叿鐢ㄤ簬瑭曚及:RCM6600W 鏁�(sh霉)鎿�(j霉)閫熺巼:20 Mbps, 40 Mbps 鎺ュ彛椤炲瀷:802.11 b/g, Ethernet 宸ヤ綔闆绘簮闆诲:3.3 V
DS3184N 鍔熻兘鎻忚堪:缍�(w菐ng)绲℃帶鍒跺櫒鑸囪檿鐞嗗櫒 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray
DS3184N+ 鍔熻兘鎻忚堪:缍�(w菐ng)绲℃帶鍒跺櫒鑸囪檿鐞嗗櫒 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:鍚� 鍒堕€犲晢:Micrel 鐢�(ch菐n)鍝�:Controller Area Network (CAN) 鏀剁櫦(f膩)鍣ㄦ暩(sh霉)閲�: 鏁�(sh霉)鎿�(j霉)閫熺巼: 闆绘簮闆绘祦锛堟渶澶у€硷級:595 mA 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:PBGA-400 灏佽:Tray