
DS3181/DS3182/DS3183/DS3184
28
6.3 DS3/E3 Internal Fractional (Subrate) ATM/Packet Mode
DS3/E3 Internal Fractional Mode allows subrate datastreams to be inserted into a DS3 or E3 line, with the
fractional overhead internally controlled. Major functional blocks for the DS3/E3 Internal Fractional Mode are shown
The “-OHM” modes are not allowed in fractional framing modes since the user is not able to distinguish between
internal framing overhead and external framing overhead bit locations.
Table 6-3. DS3/E3 Internal Fractional (IFRAC) ATM/Packet Mode Configuration Registers
MODE
FM[5:0]
SIM[1:0]
PMCPE
PORT.CR2
UTOPIA L2 ATM
0XX010
00
X
UTOPIA L3 ATM
0XX010
01
X
POS-PHY L2 ATM
0XX010
10
1
POS-PHY L3 ATM
0XX010
11
1
POS-PHY L2 Packet
0XX010
10
0
POS-PHY L3 Packet
0XX010
11
0
Figure 6-3. DS3/E3 Internal Fractional ATM/Packet Mode
RLCLKn
RXPn
RXNn
TPOSn/
TDATn
TNEGn/
TOHMOn/
TLCLKn
DS3/E3
Transmit
LIU
IEEE P1149.1
JTAG Test
Access Port
Microprocessor
Interface
HDLC
FEAC
TXPn
TXNn
LLB
DL
B
DS3 / E3
Transmit
Formatter
DS3 / E3
Receive
Framer
Trail
Trace
Buffer
Tx Cell
Processor
Tx
FIFO
Sy
stem
Inte
rf
ace
Rx Cell
Processor
Rx
FIFO
RO
Hn
ROH
C
LKn
RO
H
S
O
F
n
TO
H
n
TO
H
C
LK
n
TO
H
S
O
F
n
TC
LK
In
Tx Packet
Processor
SL
B
Rx Packet
Processor
DS3/E3
Receive
LIU
TAIS
TUA1
TOHE
Nn
Clock Rate
Adapter
TX BERT
RX BERT
CLKA
CLKB
CLK
C
PL
B
AL
B
T
O
HMIn
/T
S
O
F
In
UA1
GEN
RDATn
RPOSn/
RNEGn/
RLCVn/
ROHMIn
RS
T
B3ZS/
HDB3
Encoder
B3ZS/
HDB3
Decoder
RX FRAC
RC
LK
O
n/
R
GC
LK
n
RS
ER
n
RFOHE
N
On
TX FRAC
T
F
O
HE
NO
n
TF
O
H
n
T
C
LK
On
/T
GCLK
n
n = port # (1-4)