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參數資料
| 型號： | DS3112N |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數： | 51/134頁 |
| 文件大?。?/td> | 900K |
| 代理商： | DS3112N |
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DS3112
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2.5 LOW SPEED (T1 OR E1) RECEIVE PORT SIGNAL DESCRIPTION
Signal Name:
LRDAT1 to LRDAT28
Signal Description:
Low Speed (T1 or E1) Receive Serial Data Outputs
Signal Type:
Output
These output signals present the demultiplexed serial data for the 28 T1 data streams or the 16/21 E1 data
streams. Data can be clocked out of the device either on rising edges (normal clock mode) or falling
edges (inverted clock mode) of the associated LRCLK. This option is controlled via the LRCLKI control
bit in Master Control Register 2 (see Section 4.2). Also, the data can be internally inverted before being
output if enabled via the LRDATI control bit in Master Control Register 2 (see Section 4.2). When the
device is in the E3 Mode, LRDAT17 to LRDAT28 are meaningless and should be ignored. When the
device is in the G747 Mode, LRDAT4, LRDAT8, LRDAT12, LRDAT16, LRDAT20, LRDAT24, and
LRDAT28 are meaningless and should be ignored. When the M13 / E13 multiplexer is disabled, then
these outputs are meaningless and should be ignored.
Signal Name:
LRCLK1 to LRCLK28
Signal Description:
Low Speed (T1 or E1) Receive Serial Clock Outputs
Signal Type:
Output
These output signals present the demultiplexed serial clocks for the 28 T1 data streams or the 16/21 E1
data streams. The T1 or E1 serial data streams at the associated LRDAT signals can be clocked out of the
device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of LRCLK.
This option is controlled via the LRCLKI control bit in Master Control Register 2 (see Section 4.2).
When the device is in the E3 Mode, LRCLK17 to LRCLK28 are meaningless and should be ignored.
When the device is in the G747 Mode, LRCLK4, LRCLK8, LRCLK12, LRCLK16, LRCLK20,
LRCLK24, and LRCLK28 are meaningless and should be ignored. When the M13 / E13 multiplexer is
disabled, then these outputs are meaningless and should be ignored.
Signal Name:
LRDATA / LRDATB
Signal Description:
Low Speed (T1 or E1) Receive Drop Port Serial Data Outputs
Signal Type:
Output
These two output signals present the demultiplexed serial data from one of the 28 T1 data streams or from
one of the 16/21 E1 data streams (see Section 7.4). Data can be clocked out of the device either on rising
edges (normal clock mode) or falling edges (inverted clock mode) of the associated LRCLK. This option
is controlled via the LRCLKI control bit in Master Control Register 2 (see Section 4.2). Also, the data
can be internally inverted before being output if enabled via the LRDATI control bit in Master Control
Register 2 (see Section 4.2). When the M13 / E13 multiplexer is disabled, then these outputs are
meaningless and should be ignored.
相關PDF資料 |
PDF描述 |
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| DS3112 | DATACOM, FRAMER, PBGA256 |
| DS3131 | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS3112N+ | 功能描述:網絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網絡控制器與處理器 IC RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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