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參數(shù)資料
| 型號： | DS3112N |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 45/134頁 |
| 文件大?。?/td> | 900K |
| 代理商： | DS3112N |
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DS3112
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Signal Name:
CD0 to CD15
Signal Description:
CPU Bus Data Bus
Signal Type:
Input / Output (tri-state capable)
The external Host will configure the device and obtain real time status information about the device via
these signals. When reading data from the CPU Bus, these signals will be outputs. When writing data to
the CPU Bus, these signals will become inputs. When the CPU bus is operated in the 8-bit mode
(CMS = 1), CD8 to CD15 are inactive and should be tied low.
Signal Name:
CA0 to CA7
Signal Description:
CPU Bus Address Bus
Signal Type:
Input
These input signals determine which internal device configuration register that the external Host wishes
to access. When the CPU bus is operated in the 16-bit mode (CMS = 0), CA0 is inactive and should be
tied low. When the CPU bus is operated in the 8-bit mode (CMS = 1), CA0 is the least significant
address bit.
Signal Name:
CWR* (CR/W*)
Signal Description:
CPU Bus Write Enable (CPU Bus Read/Write Select)
Signal Type:
Input
In Intel Mode (CIM = 0) this signal will determine when data is to be written to the device. In Motorola
Mode (CIM = 1), this signal will be used to determine whether a read or write is to occur.
Signal Name:
CRD* (CDS*)
Signal Description:
CPU Bus Read Enable (CPU Bus Data Strobe)
Signal Type:
Input
In Intel Mode (CIM = 0) this signal will determine when data is to be read from the device. In Motorola
Mode (CIM = 1), a rising edge will be used to write data into the device.
Signal Name:
CINT*
Signal Description:
CPU Bus Interrupt
Signal Type:
Output (open drain)
This signal is an open drain output which will be forced low if one or more unmasked interrupt sources
within the device is active. The signal will remain low until either the interrupt is serviced or masked.
Signal Name:
CCS*
Signal Description:
CPU Bus Chip Select
Signal Type:
Input
This active low signal must be asserted for the device to accept a read or write command from an external
Host.
Signal Name:
CALE
Signal Description:
CPU Bus Address Latch Enable
Signal Type:
Input
This input signal controls a latch that exists on the CA0 to CA7 inputs. When CALE is high, the latch is
transparent. The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs. In
non-multiplexed bus applications, CALE should be tied high. In multiplexed bus applications, CA[7:0]
should be tied to CD[7:0] and the falling edge of CALE will latch the address.
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| DS3112 | DATACOM, FRAMER, PBGA256 |
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| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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