參數(shù)資料
型號: DS3112
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 94/134頁
文件大?。?/td> 900K
代理商: DS3112
DS3112
62 of 134
When the FECR is configured to count LOF occurrences, the FECR increments by one each time the
device loses receive synchronization. When the FECR is configured to count framing bit errors, it can be
configured via the ECC control bit in the T3/E3 Control Register (see Section 5.2) to either continue
counting frame bit errors during a LOF or not.
Register Name:
PCR
Register Description:
T3 Parity Bit Error Count Register
Register Address:
26h
Bit #
7
654
321
0
Name
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Default
-
---
-
Bit #
15
141312
1110
9
8
Name
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
Default
-
---
-
Note: Bits that are underlined are read only; all other bits are read-write.
Bits 0 to 15 / 16-Bit T3 Parity Bit Error Counter (PE0 to PE15). These bits report the number of T3
Parity Bit errors. In the E3 Mode, this counter is meaningless and should be ignored. A Parity Bit error
is defined as an occurrence when the two Parity Bits do not match one another or when the two Parity
Bits do not match the parity calculation made on the information bits. Via the ECC control bit in the
T3/E3 Control Register (see Section 5.2), the PCR can be configured to either continue counting parity
bit errors during a LOF or not.
Register Name:
CPCR
Register Description:
T3 C-Bit Parity Bit Error Count Register
Register Address:
28h
Bit #
765
43210
Name
CPE7
CPE6
CPE5
CPE4
CPE3
CPE2
CPE1
CPE0
Default
---
-----
Bit #
151413
121110
9
8
Name
CPE15
CPE14
CPE13
CPE12
CPE11
CPE10
CPE9
CPE8
Default
---
-----
Note: Bits that are underlined are read only; all other bits are read-write.
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