參數(shù)資料
型號: DS3112
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 112/134頁
文件大?。?/td> 900K
代理商: DS3112
DS3112
79 of 134
Bits 0 to 11 / T1 Line Loopback Command Status for Ports 17 to 28 (LLB17 to LLB28). These read
only real time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is
the inverse of the C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the
C3 bit is not the inverse of the C1 and C2 bits for 5 consecutive frames. LLB17 corresponds to T1/E1
Port 17, LLB18 corresponds to T1/E1 Port 18, and so on. The setting of any of the bits in T1LBSR1 or
T1LBSR2 can cause a hardware interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR)
is set to a one. In the E3 and G747 Modes, these bits are meaningless and should be ignored.
T1LBSR1 and T1LBSR2 Status Bit Flow Figure 7.3A
7.4 T1 / E1 DROP AND INSERT CONTROL REGISTER DESCRIPTION
Register Name:
T1E1SDP
Register Description:
T1/E1 Select Register for Receive Drop Ports A and B
Register Address:
60h
Bit #
765
43210
Name
n/a
DPAS4
DPAS3
DPAS2
DPAS1
DPAS0
Default
-
00000
Bit #
151413
121110
9
8
Name
n/a
DPBS4
DPBS3
DPBS2
DPBS1
DPBS0
Default
-
00000
Note: Bits that are underlined are read only; all other bits are read-write.
LLB1
(T1LBSR1
Bit 0)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
OR
Mask
T1LB
(IMSR Bit 8)
INT*
Hardware
Signal
T1LB
Status Bit
(MSR Bit 8)
LLB2
(T1LBSR1
Bit 1)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
LLB28
(T1LBSR2
Bit 11)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
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