參數(shù)資料
型號： DS3112
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù)： 68/134頁
文件大?。?/td> 900K
代理商： DS3112
DS3112
39 of 134
Bit 2 / Change in BERT Status (BERT). This read only real time status bit will be set to a one if there
is a major change of status in the BERT receiver. A major change of status is defined as either a change
in the receive synchronization (i.e. the BERT has gone into or out of receive synchronization), a bit error
has been detected, or an overflow has occurred in either the Bit Counter or the Error Counter. The Host
must read the status bits of the BERT in the BERT Status Register (BERTEC0) to determine the change
of state. This bit will be cleared when the BERTEC0 is read and will not be set again until the BERT has
experienced another change of state. The setting of this status bit can cause a hardware interrupt to occur
if the BERT bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when the BERTEC0 register is read. See Figure 4.3D.
Bit 3 / Change in HDLC Status (HDLC). This read only real time status bit will be set to a one if there
is a change of status in the HDLC controller. The Host must read the status bits of the HDLC in the
HDLC Status Register (HSR) to determine the change of state. This bit will be cleared when the HSR is
read and will not be set again until the HDLC has experienced another change of state. The setting of this
status bit can cause a hardware interrupt to occur if the HDLC bit in the Interrupt Mask for MSR (IMSR)
register is set to a one. The interrupt will be allowed to clear when the HSR register is read. See
Figure 4.3E.
Bit 4 / Change in FEAC Status (FEAC). This read only real time status bit will be set to a one when
the FEAC controller has detected and verified a new Far End Alarm and Control (FEAC) 16-bit
codeword. This bit will be cleared when the FEAC Status Register (FSR) is read and will not be set again
until the FEAC controller has detected and verified another new codeword. The setting of this status bit
can cause a hardware interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is
set to a one. The interrupt will be allowed to clear when the FSR register is read.
Bit 5 / Change in T2/E2 LOF or AIS Status (T2E2SR1). This read only real time status bit will be set
to a one when one or more of the T2/E2/G747 framers have detected a change in either Loss Of Frame
(LOF) or Alarm Indication Signal (AIS). See the T2E2SR1 register description in Section 6.3 for more
details. This bit will be cleared when the T2E2SR1 register is read. The setting of this status bit can
cause a hardware interrupt to occur if the T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is
set to a one. The interrupt will be allowed to clear when the T2E2SR1 register is read. See Figure 4.3F.
Bit 6 / Change in T2/E2 RAI Status (T2E2SR2). This read only real time status bit will be set to a one
when one or more of the T2/E2/G747 framers have detected a change in the detection of the Remote
Alarm Indication (RAI) signal. See the T2E2SR2 register description in Section 6.3 for more details.
This bit will be cleared when the T2E2SR2 register is read. The setting of this status bit can cause a
hardware interrupt to occur if the T2E2SR2 bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when the T2E2SR2 register is read. See Figure 4.3G.
Bit 8 / T1 Loopback Detected (T1LB). This read only real time status bit will be set to a one when one
or more of the T2 framers have detects an active T1 loopback command. See the T1LBSR1 and
T1LBSR2 register descriptions in Section 7.3 for more details. This bit will be cleared when the T1
loopback command is no longer active on any of the lines. The setting of this status bit can cause a
hardware interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
The interrupt will be allowed to clear when the none of the T2 framers detects an active T1 loopback
command. See Figure 4.3H.
相關PDF資料
PDF描述
DS3131 SPECIALTY TELECOM CIRCUIT, PBGA256
DS3134 DATACOM, FRAMER, PBGA256
DS3150QN DATACOM, PCM TRANSCEIVER, PQCC28
DS3150Q DATACOM, PCM TRANSCEIVER, PQCC28
DS3150TN DATACOM, PCM TRANSCEIVER, PDIP48
相關代理商/技術參數(shù)
參數(shù)描述
DS3112+ 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112+W 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112D1+ 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112DK 功能描述:網(wǎng)絡開發(fā)工具 DS3112 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*