7.6 Information Registers Information registers operate the same as status registers except they " />
參數(shù)資料
型號(hào): DS26502LN+
廠商: Maxim Integrated Products
文件頁數(shù): 59/125頁
文件大小: 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26502 T1/E1/J1/64KCC BITS Element
39 of 125
7.6 Information Registers
Information registers operate the same as status registers except they cannot cause interrupts. INFO3
register is a read-only register and it reports the status of the E1 synchronizer in real time. INFO3
information bits are not latched, and it is not necessary to precede a read of these bits with a write.
7.7 Interrupt Information Registers
The Interrupt Information Registers provide an indication of which Status Registers (SR1 through SR4)
are generating an interrupt. When an interrupt occurs, the host can read IIR to quickly identify which of
the three status registers are causing the interrupt.
Register Name:
IIR
Register Description:
Interrupt Information Register
Register Address:
13h
Bit #
7
6
5
4
3
2
1
0
Name
SR4
SR3
SR2
SR1
Default
0
HW
Mode
X
Bit 0: Status Register 1 (SR1)
0 = Status Register 1 interrupt not active.
1 = Status Register 1 interrupt active.
Bit 1: Status Register 2 (SR2)
0 = Status Register 1 interrupt not active.
1 = Status Register 1 interrupt active.
Bit 2: Status Register 3 (SR3)
0 = Status Register 1 interrupt not active.
1 = Status Register 1 interrupt active.
Bit 3: Status Register 4 (SR4)
0 = Status Register 1 interrupt not active.
1 = Status Register 1 interrupt active.
Bits 4 to 7: Unused
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