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參數(shù)資料
| 型號(hào)： | DS26502LN+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 109/125頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類(lèi)型： | BITS 元件，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | T1/E1 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:3 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 6.312MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 1430 (CN2011-ZH PDF) |
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DS26502 T1/E1/J1/64KCC BITS Element
84 of 125
Register Name:
LIC2
Register Description:
Line Interface Control 2
Register Address:
31h
Bit #
7
6
5
4
3
2
1
0
Name
JACKS1
LIRST
IBPV
TAIS
JACKS0
RCCFE
SCLD
CLDS
Default
0
HW
Mode
0
TAIS
PIN 10
JACKS
PIN 46
0
Bit 0: Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver.
When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7 = 0, then the device will generate a square wave at the TTIP and
TRING outputs instead of a normal waveform. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.7
≠ 0, then the device
will force TTIP and TRING outputs to become open-drain drivers instead of their normal push-pull operation. This bit should
be set to zero for normal operation of the device. Note: This bit should be set = 0 in 64KCC and 6312kHz transmit modes.
Bit 1: Short Circuit Limit Disable (in E1 mode) (SCLD). Controls the 50mA (rms) current limiter. Note: Not applicable in
6312kHz mode.
0 = enable 50mA current limiter
1 = disable 50mA current limiter
Bit 2: Receive Composite Clock Filter Enable (RCCFE). (64KCC mode only) Setting this bit will enable the PLL filter on
the received 64kHz composite clock. Note: the 8kHz and 400Hz output are not filtered.
0 = Receive Composite Clock Filter Disabled
1 = Receive Composite Clock Filter Enabled
Bit 3: Jitter Attenuator Clock Select 0 (JACKS0). This bit, along with JACKS1 (LIC2.7), MPS0 (LIC4.6), and MPS1
(LIC4.7), controls the source for JA CLOCK from the MCLK pin. Note: This bit must be configured even if the jitter
attenuator is disabled. The clock and data recovery engine also uses the JA CLOCK. Setting this bit enables the 2.048MHz to
1.544MHz conversion PLL for T1 applications. See the table in the LIC4 register description for more details on setting up the
JA CLOCK source.
0 = 2.048MHz to 1.544MHz PLL bypassed
1 = 2.048MHz to 1.544MHz PLL enabled
Bit 4: Transmit Alarm Indication Signal (TAIS)
0 = transmit an unframed all-ones code
1 = transmit data normally
Bit 5: Insert BPV (IBPV). A zero-to-one transition on this bit will cause a single BPV to be inserted into the transmit data
stream. Once this bit has been toggled from a zero to a one, the device waits for the next occurrence of three consecutive ones
to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Note: This function not
supported in 64KCC and 6312kHz modes.
Bit 6: Line Interface Reset (LIRST). Setting this bit from a zero to a one will initiate an internal reset that resets the clock
recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on power-up. Must be cleared and
set again for a subsequent reset.
Bit 7: Jitter Attenuator Clock Select 1 (JACKS1). This bit, along with JACKS0 (LIC2.3), MPS0 (LIC4.6), and MPS1
(LIC4.7), controls the source for JA CLOCK from the MCLK pin. Note: This bit must be configured even if the jitter
attenuator is disabled. The clock and data recovery engine also uses the JA CLOCK. Setting this bit enables the 12.8MHz to
2.048MHz conversion PLL. See the table in the LIC4 register description for more details on setting up the JA CLOCK source.
0 = 12.8MHz to 2.048MHz PLL bypassed
1 = 12.8MHz to 2.048MHz PLL enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS26502LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS26503 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:T1/E1/J1/64KCC BITS Element |
| DS26503_07 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:T1/E1/J1 BITS Element |
| DS26503DK | 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 DS26503 Dev Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類(lèi)型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| DS26503L | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 E1-T1-J1 Bits Element RoHS:否 制造商:Micrel 類(lèi)型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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