參數(shù)資料
型號(hào): DS26502LN+
廠商: Maxim Integrated Products
文件頁數(shù): 122/125頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: BITS 元件,多路復(fù)用器
PLL:
主要目的: T1/E1
輸入: 時(shí)鐘
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:3
差分 - 輸入:輸出: 無/無
頻率 - 最大: 6.312MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26502 T1/E1/J1/64KCC BITS Element
96 of 125
15. 64kHz SYNCHRONIZATION INTERFACE
The 64kHz synchronization interface conforms to G.703 requirements for Centralized Timing (option A),
Contradirectional Timing, and 64kHz Appendix II. It consists of a composite clock, where a 64kHz clock
signal is generated or decoded, along with embedded frequencies of 8kHz and 400Hz. Those signals
consist of AMI code with an 8kHz bipolar violation removed at every 400Hz. There are two separate
modes referred to in the specification, one with both the 64kHz clock and the 8kHz clock, and the second
with the 64kHz clock, the 8kHz clock, and the 400Hz clock.
Figure 15-1. 64kHz Composite Clock Mode Signal Format
15.1 Receive 64kHz Synchronization Interface Operation
In the receive path, the three clock frequencies are decoded from the AMI waveform with bipolar
violations that is received at the LIU interface. The 8kHz frequency and the 400Hz frequency are decoded
from the presence or absence of bipolar violations as described in G.703.
Table 15-1. Specification of 64kHz Clock Signal at Input Port
Frequency
a) 64kHz + 8kHz or
b) 64kHz + 8kHz + 400Hz
Signal format
a) AMI with 8kHz bipolar violation,
b) AMI with 8kHz bipolar violation removed at every 400Hz
Alarm condition
Alarm should not be occurred against the amplitude ranged
0.63-1.1 V0-P
Violation
No
Violation
No
Violation
125 us
8 kHz
400 Hz
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