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參數(shù)資料
| 型號： | DS21554L |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Interface |
| 英文描述： | DATACOM, PCM TRANSCEIVER, PQFP100 |
| 封裝： | 14 X 14 MM, LQFP-100 |
| 文件頁數(shù)： | 99/117頁 |
| 文件大?。?/td> | 698K |
| 代理商： | DS21554L |
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DS21354 & DS21554
82 of 117
SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two
functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering
with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows
the device to shift data into the boundary scan register via JTDI using the Shift-DR state.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the
instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting
the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
HIGHZ
All digital outputs of the device will be placed in a high impedance state. The BYPASS register will be
connected between JTDI and JTDO.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code will be loaded into the identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16
bits for the device and 4 bits for the version. See Table 17-2. Table 17-3 lists the device ID codes for the
SCT devices.
ID CODE STRUCTURE Table 17-2
MSB
LSB
Version
Contact Factory
Device ID
JEDEC
1
4 bits
16bits
00010100001
1
DEVICE ID CODES Table 17-3
DEVICE
16-BIT ID
DS21354
0005h
DS21554
0003h
DS21352
0004h
DS21552
0002h
相關PDF資料 |
PDF描述 |
|---|---|
| DS21554LN | DATACOM, PCM TRANSCEIVER, PQFP100 |
| DS2155G | DATACOM, FRAMER, PBGA100 |
| DS21600SN | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| DS21600N | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8 |
| DS2155LN | DATACOM, FRAMER, PQFP100 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS21554L+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554LB | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554LB+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554LBN | 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554LBN+ | 功能描述:網(wǎng)絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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