參數(shù)資料
型號(hào): DS21554L
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 40/117頁
文件大?。?/td> 698K
代理商: DS21554L
DS21354 & DS21554
29 of 117
ADDRESS
R/W
REGISTER NAME
REGISTER
ABBREVIATION
B1
R/W
HDLC Status Register
HSR
B2
R/W
HDLC Interrupt Mask Register
HIMR
B3
R/W
Receive HDLC Information Register
RHIR
B4
R/W
Receive HDLC FIFO Register
RHFR
B5
R/W
Interleave Bus Operation Register
IBO
B6
R/W
Transmit HDLC Information Register
THIR
B7
R/W
Transmit HDLC FIFO Register
THFR
B8
R/W
Receive HDLC DS0 Control Register 1
RDC1
B9
R/W
Receive HDLC DS0 Control Register 2
RDC2
BA
R/W
Transmit HDLC DS0 Control Register 1
TDC1
BB
R/W
Transmit HDLC DS0 Control Register 2
TDC2
BC
-
Not used
(set to 00h)
BD
-
Not used
(set to 00h)
BE
-
Not used
(set to 00h)
BF
-
Not used
(set to 00h)
NOTES:
1. Test Registers are used only by the factory; these registers must be cleared (set to all zeros) on
power– up initialization to insure proper operation.
2. Register banks Cxh, Dxh, Exh, and Fxh are not accessible.
6 CONTROL, ID, AND TEST REGISTERS
The operation of the DS21354/554 is configured via a set of ten control registers. Typically, the control
registers are only accessed when the system is first powered up. Once the device has been initialized, the
control registers will only need to be accessed when there is a change in the system configuration. There
are two Receive Control Register (RCR1 and RCR2), two Transmit Control Registers (TCR1 and TCR2),
and six Common Control Registers (CCR1 to CCR6). Each of the ten registers are described in this
section.
There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a one indicating that an E1 SCT is present. The next 3 MSBs are used to indicate which E1
device is present; DS2154, DS21354, or DS21554. The T1 pin–for–pin compatible SCTs will have a
logic zero in the MSB position with the following 3 MSBs indicating which T1 SCT is present; DS2152,
DS21352, or DS21552. Table 4-1 represents the possible variations of these bits and the associated SCT.
DEVICE ID BIT MAP Table 6-1
SCT
T1/E1
bit 6
bit 5
bit 4
DS2152
0
DS21352
0
1
DS21552
0
1
0
DS2154
1
0
DS21354
1
0
1
DS21554
1
0
1
0
The lower four bits of the IDR are used to display the die revision of the chip.
相關(guān)PDF資料
PDF描述
DS21554LN DATACOM, PCM TRANSCEIVER, PQFP100
DS2155G DATACOM, FRAMER, PBGA100
DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
DS2155LN DATACOM, FRAMER, PQFP100
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