欧产日产国产精品,国产欧美精品一区AⅤ影院,久久精品无码av一区二区三区

您好，
買賣IC網(wǎng)歡迎您。
請(qǐng)登錄
免費(fèi)注冊(cè)

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄97866 > DS21554L (DALLAS SEMICONDUCTOR) DATACOM, PCM TRANSCEIVER, PQFP100 PDF資料下載

參數(shù)資料

型號(hào)：	DS21554L
廠商：	DALLAS SEMICONDUCTOR
元件分類：	Digital Transmission Interface
英文描述：	DATACOM, PCM TRANSCEIVER, PQFP100
封裝：	14 X 14 MM, LQFP-100
文件頁(yè)數(shù)：	71/117頁(yè)
文件大?。?/td>	698K
代理商：	DS21554L

第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)當(dāng)前第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)

DS21354 & DS21554

57 of 117

14.1 Hardware Scheme

On the receive side, all of the received data is reported at the RLINK pin. Via RCR2, the user can control

the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can

be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will

identify the Si bits. See Section 19.1 for detailed timing.

On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see

Section 14.2 for details) or from the external TLINK pin. Via TCR2, the framer can be programmed to

source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits

through the framer without them being altered, then the device should be set up to source all five Sa bits

via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the

TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data flow

diagram in Section 19.2 for examples.

14.2 Internal Register Scheme Based On Double–Frame

On the receive side, the RAF and RNAF registers will always report the data as it received in the

Additional and International bit locations. The RAF and RNAF registers are updated with the setting of

the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to

read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost.

On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit

Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the

TAF and TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data

in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from

the TSER pin, (2) in the CRC4 mode, or (3) have automatic E–bit insertion enabled. Data in the Sa bit

position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to one (please see Section 14.1

for details). Please see the register descriptions for TCR1 and TCR2 and Figure 19-15 for more details.

RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)

(MSB)

(LSB)

110

SYMBOL

POSITION NAME AND DESCRIPTION

RAF.7

International Bit.

0RAF.6