參數(shù)資料
型號: DS21554L
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 82/117頁
文件大?。?/td> 698K
代理商: DS21554L
DS21354 & DS21554
67 of 117
SYMBOL
POSITION NAME AND DESCRIPTION
1 = route DS0 channels into the HDLC controller. RDC1.5 is used to
determine how the DS0 channels are selected.
RDS0M
RDC1.5
DS0 Selection Mode.
0 = utilize the RD0 to RD4 bits to select which single DS0 channel to use.
1 = utilize the RCHBLK control registers to select which DS0 channels to
use.
RD4
RDC1.4
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
RD3
RDC1.3
DS0 Channel Select Bit 3.
RD2
RDC1.2
DS0 Channel Select Bit 2.
RD1
RDC1.1
DS0 Channel Select Bit 1.
RD0
RDC1.0
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address=B9 Hex)
(MSB)
(LSB)
RDB8
RDB7
RDB6
RDB5
RDB4
RDB3
RDB2
RDB1
SYMBOL
POSITION NAME AND DESCRIPTION
RDB8
RDC2.7
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit
from being used.
RDB7
RDC2.6
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used.
RDB6
RDC2.5
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used.
RDB5
RDC2.4
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used.
RDB4
RDC2.3
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used.
RDB3
RDC2.2
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used.
RDB2
RDC2.1
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used.
RDB1
RDC2.0
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit
from being used.
TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address=BA Hex)
(MSB)
(LSB)
THE
TSaDS
TDS0M
TD4
TD3
TD2
TD1
TD0
SYMBOL
POSITION NAME AND DESCRIPTION
THE
TDC1.7
Transmit HDLC Enable.
0 = disable HDLC controller (no data inserted by HDLC controller into
the transmit data stream)
1 = enable HDLC controller to allow insertion of HDLC data into either
the Sa position or multiple DS0 channels as defined by TDC1 (see bit
definitions below).
TSaDS
TDC1.6
Transmit Sa Bit / DS0 Select. This bit is ignored if TDC1.7 is set to zero.
0 = route Sa bits from the HDLC controller. TD0 to TD4 defines which Sa
bits are to be routed. TD4 corresponds to Sa4, TD3 to Sa5, TD2 to Sa6,
TD1 to Sa7 and TD0 to Sa8.
1 = route DS0 channels from the HDLC controller. TDC1.5 is used to
determine how the DS0 channels are selected.
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