參數(shù)資料
型號(hào): DS21554L
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Interface
英文描述: DATACOM, PCM TRANSCEIVER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 56/117頁
文件大?。?/td> 698K
代理商: DS21554L
DS21354 & DS21554
43 of 117
SYMBOL
POSITION NAME AND DESCRIPTION
TAF
SR2.3
Transmit Align Frame. Set every 250 ns at the beginning of align
frames. Used to alert the host that the TAF and TNAF registers need to
be updated.
LOTC
SR2.2
Loss of Transmit Clock. Set when the TCLK pin has not transitioned
for one channel time (or 3.9 ns). Will force the LOTC pin high if enabled
via TCR2.0.
RCMF
SR2.1
Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will
continue to be set every 2 ms on an arbitrary boundary if CRC4 is
disabled.
TSLIP
SR2.0
Transmit Elastic Store Slip. Set when the elastic store has either
repeated or deleted a frame of data.
IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)
(MSB)
(LSB)
RSA1
RDMA
RSA0
RSLIP
RUA1
RRA
RCL
RLOS
SYMBOL
POSITION NAME AND DESCRIPTION
RSA1
IMR1.7
Receive Signaling All Ones / Signaling Change.
0 = interrupt masked
1 = interrupt enabled
RDMA
IMR1.6
Receive Distant MF Alarm.
0 = interrupt masked
1 = interrupt enabled
RSA0
IMR1.5
Receive Signaling All Zeros / Signaling Change.
0 = interrupt masked
1 = interrupt enabled
RSLIP
IMR1.4
Receive Elastic Store Slip Occurrence.
0 = interrupt masked
1 = interrupt enabled
RUA1
IMR1.3
Receive Unframed All Ones.
0 = interrupt masked
1 = interrupt enabled
RRA
IMR1.2
Receive Remote Alarm.
0 = interrupt masked
1 = interrupt enabled
RCL
IMR1.1
Receive Carrier Loss.
0 = interrupt masked
1 = interrupt enabled
RLOS
IMR1.0
Receive Loss of Sync.
0 = interrupt masked
1 = interrupt enabled
相關(guān)PDF資料
PDF描述
DS21554LN DATACOM, PCM TRANSCEIVER, PQFP100
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DS21600SN PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
DS21600N PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP8
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