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參數(shù)資料
| 型號(hào)： | DS21552LN |
| 英文描述： | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers |
| 中文描述： | 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器 |
| 文件頁數(shù)： | 80/137頁 |
| 文件大?。?/td> | 1094K |
| 代理商： | DS21552LN |
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DS21352/DS21552
80 of 137
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address=93 Hex)
(MSB)
TDB8
(LSB)
TDB1
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
SYMBOL
POSITION
NAME AND DESCRIPTION
TDB8
TDC2.7
DS0 Bit 8 Suppress Enable.
MSB of the DS0. Set to one to stop this bit from
being used.
DS0 Bit 7 Suppress Enable.
Set to one to stop this bit from being used.
DS0 Bit 6 Suppress Enable.
Set to one to stop this bit from being used.
DS0 Bit 5 Suppress Enable.
Set to one to stop this bit from being used.
DS0 Bit 4 Suppress Enable.
Set to one to stop this bit from being used.
DS0 Bit 3 Suppress Enable.
Set to one to stop this bit from being used.
DS0 Bit 2 Suppress Enable.
Set to one to stop this bit from being used.
DS0 Bit 1 Suppress Enable.
LSB of the DS0. Set to one to stop this bit from
being used.
TDB7
TDB6
TDB5
TDB4
TDB3
TDB2
TDB1
TDC2.6
TDC2.5
TDC2.4
TDC2.3
TDC2.2
TDC2.1
TDC2.0
15.4 LEGACY FDL SUPPORT
15.4.1 OVERVIEW
In order to provide backward compatibility to the older DS2152 device, the DS21352/552 maintains the
circuitry that existed in the previous generation of the T1 Quad Framer. Sections 15.4.2 and 15.4.3 cover
the circuitry and operation of this legacy functionality. In new applications, it is recommended that the
HDLC controller and BOC controller described in Section 15.3 are used. On the receive side, it is
possible to have both the new HDLC/BOC controller and the legacy hardware working at the same time.
On the transmit side the HDLC/BOC controller can be assigned to a DSO while the legacy function
supports the FDL via software. Software for supporting the legacy functions is available from Dallas
Semiconductor.
15.4.2 RECEIVE SECTION
In the receive section, the recovered FDL bits or Fs bits are shifted bit–by–bit into the Receive FDL
register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2 ms (8 times 250 us). The framer
will signal an external microcontroller that the buffer has filled via the SR2.4 bit. If enabled via IMR2.4,
the INT pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2 ms to
read this data before it is lost. If the byte in the RFDL matches either of the bytes programmed into the
RFDLM1 or RFDLM2 registers, then the SR2.2 bit will be set to a one and the INT pin will toggled low
if enabled via IMR2.2. This feature allows an external microcontroller to ignore the FDL or Fs pattern
until an important event occurs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21354 | MTTF is frequently used interchangeably with MTBF |
| DS21354L | 3.3V/5V E1 Single-Chip Transceivers |
| DS21354LN | 3.3V/5V E1 Single-Chip Transceivers |
| DS21354 | 3.3V/5V E1 Single-Chip Transceivers |
| DS2152LN | Enhanced T1 Single-Chip Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21552LN+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554 | 制造商:Maxim Integrated Products 功能描述: |
| DS21554G | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS21554GN | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| DS21554L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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