參數(shù)資料
型號(hào)： DS21552LN
英文描述： 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers
中文描述： 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器
文件頁(yè)數(shù)： 44/137頁(yè)
文件大小： 1094K
代理商： DS21552LN
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)當(dāng)前第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)
DS21352/DS21552
44 of 137
RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
(MSB)
COFA
(LSB)
FBE
8ZD
16ZD
RESF
RESE
SEFE
B8ZS
SYMBOL
POSITION
NAME AND DESCRIPTION
COFA
RIR1.7
Change of Frame Alignment.
Set when the last resync resulted in a change of frame
or multiframe alignment.
Eight Zero Detect.
Set when a string of at least eight consecutive zeros (regardless of
the length of the string) have been received at RPOSI and RNEGI.
Sixteen Zero Detect.
Set when a string of at least sixteen consecutive zeros (regardless
of the length of the string) have been received at RPOSI and RNEGI.
Receive Elastic Store Full.
Set when the receive elastic store buffer fills and a frame
is deleted.
Receive Elastic Store Empty.
Set when the receive elastic store buffer empties and a
frame is repeated.
Severely Errored Framing Event.
Set when 2 out of 6 framing bits (Ft or FPS) are
received in error.
B8ZS Code Word Detect.
Set when a B8ZS code word is detected at RPOSI and
RNEGI independent of whether the B8ZS mode is selected or not via CCR2.6. Useful
for automatically setting the line coding.
Frame Bit Error.
Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
8ZD
RIR1.6
16ZD
RIR1.5
RESF
RIR1.4
RESE
RIR1.3
SEFE
RIR1.2
B8ZS
RIR1.1
FBE
RIR1.0
RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)
(MSB)
RLOSC
LRCLC
TESF
TESE
(LSB)
TPDV
TSLIP
RBLC
RPDV
SYMBOL
POSITION
NAME AND DESCRIPTION
RLOSC
RIR2.7
Receive Loss of Sync Clear.
Set when the framer achieves synchronization; will
remain set until read.
Line Interface Receive Carrier Loss Clear.
Set when the carrier signal is restored;
will remain set until read. See Table 7-2.
Transmit Elastic Store Full.
Set when the transmit elastic store buffer fills and a frame
is deleted.
Transmit Elastic Store Empty.
Set when the transmit elastic store buffer empties and a
frame is repeated.
Transmit Elastic Store Slip Occurrence.
Set when the transmit elastic store has either
repeated or deleted a frame.
Receive Blue Alarm Clear.
Set when the Blue Alarm (AIS) is no longer detected; will
remain set until read. See Table 7-2.
Receive Pulse Density Violation.
Set when the receive data stream does not meet the
ANSI T1.403 requirements for pulse density.
Transmit Pulse Density Violation.
Set when the transmit data stream does not meet
the ANSI T1.403 requirements for pulse density.
RIR3: RECEIVE INFORMATION REGISTER 3 (Address=10 Hex)
LRCLC
RIR2.6
TESF
RIR2.5
TESE
RIR2.4
TSLIP
RIR2.3
RBLC
RIR2.2
RPDV
RIR2.1
TPDV
RIR2.0
(MSB)
RL1
(LSB)
–
RL0
JALT
LORC
FRCL
–
–
SYMBOL
POSITION
NAME AND DESCRIPTION
RL1
RIR3.7
Receive Level Bit 1.
SeeTable 7-1.
RL0
RIR3.6
Receive Level Bit 0.
See Table 7-1.
JALT
RIR3.5
Jitter Attenuator Limit Trip.
Set when the jitter attenuator FIFO reaches to within 4
相關(guān)PDF資料
PDF描述
DS21354 MTTF is frequently used interchangeably with MTBF
DS21354L 3.3V/5V E1 Single-Chip Transceivers
DS21354LN 3.3V/5V E1 Single-Chip Transceivers
DS21354 3.3V/5V E1 Single-Chip Transceivers
DS2152LN Enhanced T1 Single-Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21552LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21554 制造商:Maxim Integrated Products 功能描述:
DS21554G 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
DS21554GN 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:*
DS21554L 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*