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參數資料
| 型號： | DS21552LN |
| 英文描述： | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers |
| 中文描述： | 3.3 DS21352及5V DS21552 T1單芯片收發(fā)器 |
| 文件頁數： | 83/137頁 |
| 文件大小： | 1094K |
| 代理商： | DS21552LN |
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DS21352/DS21552
83 of 137
16. LINE INTERFACE FUNCTION
The line interface function in the DS21352/552 contains three sections; (1) the receiver which handles
clock and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter
attenuator. Each of the these three sections is controlled by the Line Inter-face Control Register (LICR)
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex)
(MSB)
L2
(LSB)
TPD
L1
L0
EGL
JAS
JABDS
DJA
SYMBOL
L2
L1
L0
EGL
POSITION
LICR.7
LICR.6
LICR.5
LICR.4
NAME AND DESCRIPTION
Line Build Out Select Bit 2. Sets the transmitter build out; see Table 16-1
Line Build Out Select Bit 1. Sets the transmitter build out; see Table 16-1
Line Build Out Select Bit 0. Sets the transmitter build out; see Table 16-1
Receive Equalizer Gain Limit. 0 = –36 dB 1 = –30 dB
JAS
LICR.3
Jitter Attenuator Select. 0 = place the jitter attenuator on the receive side 1 = place
the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select 0 = 128 bits 1 = 32 bits (use for delay
sensitive applications)
Disable Jitter Attenuator. 0 = jitter attenuator enabled 1 = jitter attenuator disabled
Transmit Power Down. 0 = normal transmitter operation 1 = powers down the
transmitter and 3-states the TTIP and TRING pins
JABDS
LICR.2
DJA
TPD
LICR.1
LICR.0
16.1 RECEIVE CLOCK AND DATA RECOVERY
The DS21352/552 contains a digital clock recovery system. See Figure 3-1 and Figure 16-1 for more
details. The DS21352/552 couples to the receive T1 twisted pair via a 1:1 transformer. See for details.
The 1.544 MHz clock applied to the MCLK pin is internally multiplied by 16 via an internal PLL and fed
to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16
times oversampler which is used to recover the clock and data. This oversampling technique offers
outstanding jitter tolerance (see Figure 16-4).
Normally, the clock that is output at the RCLKO pin is the recovered clock from the T1 AMI/B8ZS
waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,
a Receive Carrier Loss (LRCL) condition will occur and the RCLKO will be sourced from the clock
applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly oversampled
digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most
applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the
Receive AC Timing Characteristics in section 24 for more details.
相關PDF資料 |
PDF描述 |
|---|---|
| DS21354 | MTTF is frequently used interchangeably with MTBF |
| DS21354L | 3.3V/5V E1 Single-Chip Transceivers |
| DS21354LN | 3.3V/5V E1 Single-Chip Transceivers |
| DS21354 | 3.3V/5V E1 Single-Chip Transceivers |
| DS2152LN | Enhanced T1 Single-Chip Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| DS21552LN+ | 功能描述:網絡控制器與處理器 IC 5V T1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21554 | 制造商:Maxim Integrated Products 功能描述: |
| DS21554G | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS21554GN | 功能描述:IC TXRX E1 1-CHIP 5V 100-BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS 產品變化通告:Product Discontinuation 06/Feb/2012 標準包裝:750 系列:* |
| DS21554L | 功能描述:網絡控制器與處理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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