參數(shù)資料
型號(hào): DRV591GQE
英文描述: Analog IC
中文描述: 模擬IC
文件頁數(shù): 16/19頁
文件大小: 256K
代理商: DRV591GQE
DRV591
SLOS389
NOVEMBER 2001
16
www.ti.com
APPLICATION INFORMATION
printed circuit board (PCB) layout considerations
Since the DRV591 is a high-current switching device, a few guidelines for the layout of the printed-circuit board
(PCB) must be considered:
1.
Grounding.
Analog ground (AGND) and power ground (PGND) must be kept separated, ideally back to
where the power supply physically connects to the PCB, minimally back to the bulk decoupling capacitor
(10
μ
F ceramic minimum). Furthermore, the PowerPAD ground connection should be made to AGND, not
PGND. Ground planes are not recommended for AGND or PGND, traces should be used to route the
currents. Wide traces (100 mils) should be used for PGND while narrow traces (15 mils) should be used
for AGND.
2.
Power supply decoupling.
A small 0.1
μ
F to 1
μ
F ceramic capacitor should be placed as close to each
set of PVDD pins as possible, connecting from PVDD to PGND. A 0.1
μ
F to 1
μ
F ceramic capacitor should
also be placed close to the AVDD pin, connecting from AVDD to AGND. A bulk decoupling capacitor of at
least 10
μ
F, preferably ceramic, should be placed close to the DRV591, from PVDD to PGND. If power
supply lines are long, additional decoupling may be required.
3.
Power and output traces.
The power and output traces should be sized to handle the desired maximum
output current. The output traces should be kept as short as possible to reduce EMI, i.e., the output filter
should be placed as close to the DRV591 outputs as possible.
4.
PowerPAD.
The DRV591 in the Quad Flatpack package uses TI
s PowerPAD technology to enhance the
thermal performance. The PowerPAD is physically connected to the substrate of the DRV591 silicon, which
is connected to AGND. The PowerPAD ground connection should therefore be kept separate from PGND
as described above. The pad underneath the AGND pin may be connected underneath the device to the
PowerPAD ground connection for ease of routing. For additional information on PowerPAD PCB layout,
refer to the
PowerPAD Thermally Enhanced Package
application note, TI literature number SLMA002.
5.
Thermal performance.
For proper thermal performance, the PowerPAD must be soldered down to a
thermal land, as described in the
PowerPAD Thermally Enhanced Package
application note, TI literature
number SLMA002. In addition, at high current levels (greater than 2 A) or high ambient temperatures
(greater than 25
°
C), an internal plane may be used for heat sinking. The vias under the PowerPAD should
make a solid connection, and the plane should not be tied to ground except through the PowerPAD
connection, as described above.
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