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參數(shù)資料
| 型號(hào)： | DNC3X3125 |
| 廠商： | Lineage Power |
| 英文描述： | 10/100 Mbits/s Ethernet Transceiver Macrocell(10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 29/32頁 |
| 文件大小： | 460K |
| 代理商： | DNC3X3125 |
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Advance Data Sheet
March 2000
DNC3X3125
10/100 Mbits/s Ethernet Transceiver Macrocell
29
4
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
Table 28. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
Bit
*
Type
R/W
Description
29.1 (FEF-EN)
Far-End Fault Enable
. This bit is used to enable the far-end fault detection and
transmission capability. This capability may only be used if autonegotiation is
disabled. This capability is to be used only with media which does not support
autonegotiation. Setting this bit to 1 enables far-end fault detection, and logic 0
will disable the function. Default state is 0.
Fiber-Optic Mode.
When this bit is a 1, the DNC3X3125 is in fiber-optic mode.
This bit is ORed with FX_MODE.
29.0 (FX)
R/W
Bit
*
Type
R/W
Description
30.15 (Test10TX)
When high and 10Base-T is powered up, a continuous 10 MHz signal (1111)
will be transmitted. This is only meant for testing. Default 0.
When high, all 10Base-T logic will be powered up when the link is up. Other-
wise, portions of the logic will be powered down when no data is being
received to conserve power. Default is 0.
Jabber Disable.
When this bit is 1, disables the jabber function of the
10Base-T receive. Default is 0.
Reserved.
Should be written as 0.
Enhanced Link Integrity Test Function.
When high, function is enabled.
This is ORed with the LITF_ENH input. Default is 0.
Heartbeat Enable.
When this bit is a 1, the heartbeat function will be enabled.
Valid in 10 Mbits/s mode only.
Extended Line Length Enable.
When this bit is a 1, the receive squelch lev-
els are reduced from a nominal 435 mV to 350 mV, allowing reception of sig-
nals with a lower amplitude. Valid in 10 Mbits/s mode only.
Autopolarity Function Disable.
When this bit is a 0 and the DNC3X3125 is
in 10 Mbits/s mode, the autopolarity function will determine if the TP link is
wired with a polarity reversal.
30.14 (RxPLLEn)
R/W
30.13 (JAB_DIS)
R/W
30.12:7 (Reserved)
30.6 (LITF_ENH)
R/W
R/W
30.5 (HBT_EN)
R/W
30.4 (ELL_EN)
R/W
30.3 (APF_EN)
R/W
If there is a polarity reversal, the DNC3X3125 will assert the APS bit (register
28, bit 6) and correct the polarity reversal. If this bit is a 1 and the device is in
10 Mbits/s mode, the reversal will not be corrected.
Reserved
. Should be written as 0.
Serial Select.
When this bit is set to a 1, 10 Mbits/s serial mode will be
selected. When the DNC3X3125 is in 100 Mbits/s mode, this bit will be
ignored.
No Link Pulse Mode.
Setting this bit to a 1 will allow 10 Mbits/s operation
with link pulses disabled. If the DNC3X3125 is configured for 100 Mbits/s
operation, setting this bit will not affect operation.
30.2 (RESERVED)
30.1 (SERIAL _SEL)
R/W
R/W
30.0 (ENA_NO_LP)
R/W
Register Information
(continued)
Table 27. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions
(continued)
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