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參數(shù)資料
| 型號(hào)： | DNC3X3125 |
| 廠商： | Lineage Power |
| 英文描述： | 10/100 Mbits/s Ethernet Transceiver Macrocell(10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 26/32頁 |
| 文件大?。?/td> | 460K |
| 代理商： | DNC3X3125 |
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26
DNC3X3125
10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
4
Register Information
(continued)
Table 22. MR17—Autonegotiation Read Register A
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
Table 23. MR18—Autonegotiation Read Register B
* The format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register.
R = read, W = write.
Bit
*
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
17.15-13
17.12
17.11
17.10
17.9
17.8
17.7
17.6
17.5
17.4
17.3
17.2
17.1
17.0
Reserved. Always 0.
Next Page Wait.
Wait Link_Fail_Inhibit_Wait_Timer (Link Status Check).
Wait Autoneg_Wait_Timer (Link Status Check).
Wait Break_Link_Timer (Transmit Disable).
Parallel Detection Fault.
Autonegotiation Enable.
FLP Link Good Check.
Complete Acknowledge.
Acknowledge Detect.
FLP Link Good.
Link Status Check.
Ability Detect.
Transmit Disable.
Bit
*
18.15
18.14
18.13
18.12
18.11
18.10
18.9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18.0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
Receiving FLPs
. Any of FLP Capture, Clock, Data_0, or Data_1 (FLP Rcv).
FLP Pass
(FLP Rcv).
Link Pulse Count
(FLP Rcv).
Link Pulse Detect
(FLP Rcv).
Test Pass
(NLP Rcv).
Test Fail Count
(NLP Rcv).
Test Fail Extend
(NLP Rcv).
Wait Max Timer Ack
(NLP Rcv).
Detect Freeze
(NLP Rcv).
Test Fail
(NLP Rcv).
Transmit Count Ack
(FLP Xmit).
Transmit Data Bit
(FLP Xmit).
Transmit Clock Bit
(FLP Xmit).
Transmit ability
(FLP Xmit).
Transmit Remaining Acknowledge
(FLP Xmit).
Idle
(FLP Xmit).
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