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參數(shù)資料
| 型號： | DNC3X3125 |
| 廠商： | Lineage Power |
| 英文描述： | 10/100 Mbits/s Ethernet Transceiver Macrocell(10M位/秒和100 M位/秒以太網(wǎng)收發(fā)器宏單元) |
| 中文描述： | 10/100 Mbits /秒以太網(wǎng)收發(fā)器宏單元（1000萬位/秒和100海里位/秒以太網(wǎng)收發(fā)器宏單元） |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 460K |
| 代理商： | DNC3X3125 |
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12
DNC3X3125
10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
4
Table 7. Testability Signals
Note: All TEST I/Os are preferred to be mapped out in test mode for debug access. If the chip does not have the resources to support all I/Os,
contact your Lucent representative for a list of the I/Os that are not required during test.
SERIAL_SEL
O
Serial Select.
When this signal is high, it indicates 10 Mbit/s serial mode.
When SERIAL_SEL is low, the macro is in 100 Mbits/s or 10 Mbits/s parallel
mode.
Autonegotiation Done.
This signal goes high whenever autonegotiation
has completed. It will go low if autonegotiation has to restart.
Register 20 Access.
This bus provides access to the user-defined register.
A write to this register can be through MDIO.
AUTODONE
O
R20_OUT[15:0]
O
Signal
Type
I
Description
TESTSEL[3:0]
Test Mode Select.
These pins enable the PHY to be in various test
modes: scan, analog, etc. Lucent requires access to these pins for
manufacturing testing. They should be held low for normal operation.
Test Mode Inputs.
These test inputs provide a high level of controlla-
bility to the macrocell, either as scan inputs or as digital/analog test
inputs/controls depending on the test mode selected by TESTSEL[3:0].
TESTMDC
TESTTXD[3:0]
TESTTXER
TESTTXEN
TESTCRS
TESTCOL
TESTRXCK
TESTTXCK
TESTRXD[3:0]
TESTRXER
TESTRXDV
ATBOP
ATBON
ECLP
ECLN
TESTMDIN
TESTMDOUT
TESTMDHZ
I
O
Test Mode Outputs.
These test output pins provide observability in the
form of either scan outputs or digital/analog test outputs depending on
the test mode selected by TESTSEL[3:0].
PADO
(optional)
Analog Test Output Pins
. These are used in Lucent test modes. They
should be connected to bond pads, but are not required to be
connected to package pins.
I
Test Mode MDIN, MDOUT, and MDHZ.
Input, output, and I/O control
signals from/to a bidirectional buffer.
O
O
Signal
Type
Description
Signal Information
(continued)
Table 6. Control/Status Signals
(continued)
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