
58
8Bit Single Chip Microcontroller
DMC73C167
5.7.2 Slave Mode
The DMC73C167 can be used as an I2C slave receiver and/or transmitter. The
slave address is not set by hardware but is programmable by software. There are
three peripheral registers for I2C slave operations: SCTL, SADDR, and SDATA.
5.7.2.1 Slave Control Registers
Table 5-35. P56 0138h SCTL I2C Slave Control
Bit
R
W
7
6
5
4
3
2
1
0
ENABLE
Not Used
SEL
SDIR
GCALL
INT5_2F
INT5_2C
Not Used
Bit 7
ENABLE. Enables I2C Slave Hardware (R/W).
Upon a hardware reset, this bit will be zero. After initialization of SADDR, this bit
can be set to enable the slave module. ENABLE is to be read from and written to
by software.
SEL. Device Selected (READ).
The general call address or address match will set this bit.
SDIR. Slave Data Direction (READ).
0 = Slave receiver (data read from I2C bus)
1 = Slave transmitter (data written to I2C bus)
GCALL. General Call.
0 = Normal
1 = Detects general call address.
INT5_2F. I2C Slave Interrupt Flag (READ).
This flag is identical to bit 5 of IOCTL4. The following cases will set INT5_2F and
generate an interrupt if enabled.
1) Slave transmitter mode (SDIR=1): Just after the slave address is selected (SEL=1)
2) Slave receiver mode (SDIR=0): The slave address is selected after receiving one byte.
3) After each byte of data is received or transmitted. But the interrupt will not be
generated after the last byte is transmitted because there will be no acknowledge
signal from the master.
INT5_2C. Clear I2C Slave Interrupt Flag (WRITE).
0 = No effected.
1 = Clears INT5_2 flag.
Bit 3
Bit 2
Bit 1
Bit 0
Notes:
1) Before clearing the INT5_2F bit, data must be read from or written to the
SDATA register.
2) The SCL will be pulled down when INT5_2F is set to high. But when it is cleared,
the SCL line will be released and can be controlled by the master device.
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