
54
8Bit Single Chip Microcontroller
DMC73C167
SCLK
Calculation example of SCL clock speed (Fosc:4MHz)
( 1) MOVP %F9h, HDC
FFh-F9h = 6
( 4x6+8) / 4 = 8
so hi gh durati on
w l l be 8us
( 2) MOVP %F9h, LDC
FFh - F9h = 6
( 4x6+8) / 4 = 8
so l owdurati on w l l
be 8us; but i f DTY = 1,
l owdurati on w l l be 20us
Notes:
1) By calcuration, any value can be selected except the following two values:
FFh, FEh (by design specifications).
2) The I2C bus minimum timing specification must be kept. The minimum
high/low duration is 4.0/4.7us, respectively.
3) The digital filter is contained for special user. Please set "0" for normal usage.
4) The HDC (P52) and LDC (P53) registers are not able to be read from and
written to if the ENABLE bit (P49, bit 7) is not set to 1.
5.7.1.2 Master Mode Operation
Any transfer will begin with a start condition and terminate with a stop condition.
After the start condition is generated, a slave address (the contents of MDATA) is
sent. This address is 8 bits long. Bit 0 indicates the data direction: 0 = write to slave
and 1 = read from slave. Following the address, 8-bit data is transferred as required
and then terminated by a stop condition generated by the master. However, if the
master still wants to communicate on the bus, it can generate another start condition
and address another slave without generating a stop condition (restart condition).
Various combinations of read/write formats are then possible within such a transfer.
On the DMC73C167, a hardware reset clears all bits of the master control and
status registers. To start data transfer, HDC and LDC must be set with the desired
value, and the ENABLE bit must be set to 1. The following are I2C master mode
control examples of data transfer operations.
Objective:
Send immediate hex data to Slave A: 88h, AAh
HD
LD
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