參數(shù)資料
型號: DM9000E
廠商: Electronic Theatre Controls, Inc.
英文描述: ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY
中文描述: ISA以以太網(wǎng)MAC控制器,它集成10/100網(wǎng)卡芯片
文件頁數(shù): 9/54頁
文件大?。?/td> 575K
代理商: DM9000E
DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9000-DS-F02
June 26, 2002
9
66
EECK
O
Clock to EEPROM
67
EECS
I/O
Chip Select to EEPROM
This pin is also used as a strap pin to define the LED modes.
When it is pulled high, the LED mode is mode 1; Otherwise it is mode 0
Note: The pins EECS,EECK and EEDO are all have a pulled down resistor about 60k ohm internally
5.4 Clock Interface
21
X2_25M
O
Crystal 25MHz Out
22
X1_25M
I
Crystal 25MHz In
59
CLK20MO
O
20Mhz Clock Output
It is used as the clock signal for the external MII device’s clock is 20MHz
This pin has a pulled down resistor about 60k ohm internally.
5.5 LED
I
nterface
60
SPEED100#
O
Speed LED
Its low output indicates that the internal PHY is operated in 100M/S, or it
is floating for the 10M mode of the internal PHY
Full-duplex LED
In LED mode 1, Its low output indicates that the internal PHY is operated
in full-duplex mode, or it is floating for the half-duplex mode of the internal
PHY
In LED mode 0, Its low output indicates that the internal PHY is operated
in 10M mode, or it is floating for the 100M mode of the internal PHY
Link LED
In LED mode 1, it is the combined LED of link and carrier sense signal of
the internal PHY
In LED mode 0, it is the LED of the carrier sense signal of the internal
PHY only
61
DUP#
O
62
LINK&ACT#
O
5.6 10/100 PHY/Fiber
24
SD
I
Fiber-optic Signal Detect
PECL signal, which indicates whether or not the fiber-optic receive pair is
receiving valid levels
Bandgap Ground
25
BGGND
P
26
BGRES
I/O
Bandgap Pin
27
AVDD
P
Bandgap and Guard Ring Power
28
AVDD
P
RX Power
29
RXI+
I
TP RX Input
30
RXI-
I
TP RX Input
31
AGND
P
RX Ground
32
AGND
P
TX Ground
33
TXO+
O
TP TX Output
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