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參數(shù)資料
| 型號： | DM9000E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ISA TO ETHERNET MAC CONTROLLER WITH INTEGRATED 10/100 PHY |
| 中文描述： | ISA以以太網(wǎng)MAC控制器，它集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 23/54頁 |
| 文件大?。?/td> | 575K |
| 代理商： | DM9000E |
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DM9000
ISA to Ethernet MAC controller with integrated 10/100 PHY
Final
Version: DM9000-DS-F01
April 12, 2002
23
8.1 Basic Mode Control Register (BMCR) - 00
Bit
Bit Name
0.15
Reset
Default
0, RW/SC
Description
Reset
1=Software reset
0=Normal operation
This bit sets the status and controls the PHY registers to their default
states. This bit, which is self-clearing, will keep returning a value of
one until the reset process is completed
Loopback
Loop-back control register
1 = Loop-back enabled
0 = Normal operation
In 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead
time" before any valid data appears at the MII receive outputs
Speed Select
1 = 100Mbps
0 = 10Mbps
Link speed may be selected either by this bit or by auto-negotiation.
When auto-negotiation is enabled and bit 12 is set, this bit will return
to the auto-negotiation selected media type
Auto-negotiation Enable
1 = Auto-negotiation is enabled, bit 8 and 13 will be in auto-
negotiation status
Power Down
While in the power-down state, the PHY should respond to the
management transactions. During the transition to power-down state
and while in the power-down state, the PHY should not generate
spurious signals on the MII
1=Power down
0=Normal operation
Isolate
1 = Isolates the PHY from the MII with the exception of the serial
management. (When this bit is asserted, the PHY does not respond
to the TXD [0:3], TX_EN, and TX_ER inputs, and it shall present a
high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER,
RXD[0:3], COL and CRS outputs. When PHY is isolated from the MII
it shall respond to the management transactions)
0 = Normal operation
Restart Auto-negotiation
1 = Restart auto-negotiation. Re-initiates the auto-negotiation
process. When auto-negotiation is disabled (bit 12 of this register
cleared), this bit has no function and it should be cleared. This bit is
self-clearing and it will keep returning a value of 1 until auto-
negotiation is initiated by the PHY. The operation of the auto-
negotiation process will not be affected by the management entity
that clears this bit
0 = Normal operation
0.14
Loopback
0, RW
0.13
Speed selection
1, RW
0.12
Auto-
negotiation
enable
Power down
1, RW
0.11
0, RW
0.10
Isolate
0,RW
0.9
Restart auto-
negotiation
0,RW/SC
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| DM9002CN | Quad 2-input NAND Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9000E-H | 功能描述:以太網(wǎng)開發(fā)工具 ETHERNET CONTROLLER HEADER BRD 50x40mm RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評估:KSZ8873RLL 接口類型:RMII 工作電源電壓: |
| DM9000EP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 100LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Digital IC Case Style:LQFP; No. of Pins:100; Interface Type:MII; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9000電路圖-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:型號DM9000電路圖1 |
| DM9000電路圖-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DM9000電路圖-2 |
| DM9002CJ/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad 2-input NAND Gate |
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