參數(shù)資料
型號: DK-DEV-4CGX150N
廠商: Altera
文件頁數(shù): 4/42頁
文件大?。?/td> 0K
描述: KIT DEVELOPMENT CYCLONE IV GX
應(yīng)用說明: Cyclone IV Design Guidelines
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
軟件下載: DK-DEV-4CGX150N Kit Install
特色產(chǎn)品: Cyclone? IV GX FPGA Development Kit
標(biāo)準(zhǔn)包裝: 1
系列: CYCLONE® IV GX
類型: FPGA
適用于相關(guān)產(chǎn)品: Cyclone IV GX
所含物品: 板,線纜,文檔,電源
其它名稱: 544-2713
1–12
Chapter 1: Cyclone IV Device Datasheet
Operating Conditions
December 2013
Altera Corporation
Schmitt Trigger Input
Cyclone IV devices support Schmitt trigger input on the TDI, TMS, TCK, nSTATUS,
nCONFIG
, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces
hysteresis to the input signal for improved noise immunity, especially for signals with
slow edge rate. Table 1–14 lists the hysteresis specifications across the supported
VCCIO range for Schmitt trigger inputs in Cyclone IV devices.
I/O Standard Specifications
The following tables list input voltage sensitivities (VIH and VIL), output voltage (VOH
and VOL), and current drive characteristics (IOH and IOL), for various I/O standards
supported by Cyclone IV devices. Table 1–15 through Table 1–20 provide the I/O
standard specifications for Cyclone IV devices.
Table 1–14. Hysteresis Specifications for Schmitt Trigger Input in Cyclone IV Devices
Symbol
Parameter
Conditions (V)
Minimum
Unit
VSCHMITT
Hysteresis for Schmitt trigger
input
VCCIO = 3.3
200
mV
VCCIO = 2.5
200
mV
VCCIO = 1.8
140
mV
VCCIO = 1.5
110
mV
Table 1–15. Single
-Ended I/O Standard Specifications for Cyclone IV Devices (1), (2)
I/O Standard
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOL
(mA)
IOH
(mA)
Min
Typ
Max
Min
Max
Min
Max
Min
3.3
-V LVTTL (3)
3.135
3.3
3.465
0.8
1.7
3.6
0.45
2.4
4
–4
3.3
-V LVCMOS (3)
3.135
3.3
3.465
0.8
1.7
3.6
0.2
VCCIO – 0.2
2
–2
3.0
-V LVTTL (3)
2.85
3.0
3.15
–0.3
0.8
1.7
VCCIO + 0.3
0.45
2.4
4
–4
3.0
-V LVCMOS (3)
2.85
3.0
3.15
–0.3
0.8
1.7
VCCIO + 0.3
0.2
VCCIO – 0.2
0.1
–0.1
2.5 V (3)
2.375
2.5
2.625
–0.3
0.7
1.7
VCCIO + 0.3
0.4
2.0
1
–1
1.8 V
1.71
1.8
1.89
–0.3
0.35 x
VCCIO
0.65 x
VCCIO
2.25
0.45
VCCIO
0.45
2–2
1.5 V
1.425
1.5
1.575
–0.3
0.35 x
VCCIO
0.65 x
VCCIO
VCCIO + 0.3
0.25 x
VCCIO
0.75 x
VCCIO
2–2
1.2 V
1.14
1.2
1.26
–0.3
0.35 x
VCCIO
0.65 x
VCCIO
VCCIO + 0.3
0.25 x
VCCIO
0.75 x
VCCIO
2–2
3.0-V PCI
2.85
3.0
3.15
0.3 x
VCCIO
0.5 x
VCCIO
VCCIO + 0.3 0.1 x VCCIO
0.9 x VCCIO
1.5
–0.5
3.0-V PCI-X
2.85
3.0
3.15
0.35 x
VCCIO
0.5 x
VCCIO
VCCIO + 0.3 0.1 x VCCIO
0.9 x VCCIO
1.5
–0.5
Notes to Table 1–15:
(1) For voltage
-referenced receiver input waveform and explanation of terms used in Table 1–15, refer to “Glossary” on page 1–37.
(2) AC load CL = 10 pF
(3) For more information about interfacing Cyclone IV devices with 3.3/3.0/2.5
-V LVTTL/LVCMOS I/O standards, refer to AN 447: Interfacing Cyclone III
(4) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4
mA), set the current strength settings to 4 mA or higher. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook.
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