- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17123 > DK-DEV-4CGX150N (Altera)KIT DEVELOPMENT CYCLONE IV GX PDF資料下載
參數(shù)資料
| 型號： | DK-DEV-4CGX150N |
| 廠商： | Altera |
| 文件頁數(shù)： | 35/42頁 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT CYCLONE IV GX |
| 應(yīng)用說明： | Cyclone IV Design Guidelines |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 軟件下載： | DK-DEV-4CGX150N Kit Install |
| 特色產(chǎn)品： | Cyclone? IV GX FPGA Development Kit |
| 標(biāo)準包裝： | 1 |
| 系列： | CYCLONE® IV GX |
| 類型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | Cyclone IV GX |
| 所含物品： | 板，線纜，文檔，電源 |
| 其它名稱： | 544-2713 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
1–40
Chapter 1: Cyclone IV Device Datasheet
Glossary
December 2013
Altera Corporation
T
tC
High-speed receiver and transmitter input and output clock period.
Channel-to-
channel-skew
(TCCS)
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including tCO variation and clock skew. The clock is included in the TCCS measurement.
tcin
Delay from the clock pad to the I/O input register.
tCO
Delay from the clock pad to the I/O output.
tcout
Delay from the clock pad to the I/O output register.
tDUTY
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
tFALL
Signal high-to-low transition time (80–20%).
tH
Input register hold time.
Timing Unit
Interval (TUI)
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
tINJITTER
Period jitter on the PLL clock input.
tOUTJITTER_DEDCLK
Period jitter on the dedicated clock output driven by a PLL.
tOUTJITTER_IO
Period jitter on the general purpose I/O driven by a PLL.
tpllcin
Delay from the PLL inclk pad to the I/O input register.
tpllcout
Delay from the PLL inclk pad to the I/O output register.
Transmitter
Output
Waveform
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
tRISE
Signal low-to-high transition time (20–80%).
tSU
Input register setup time.
U
——
Table 1–46. Glossary (Part 4 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
OH
Negative Channel (n) = V
OL
Ground
VOD
V
OD
V
OD
0 V
Vos
p
- n
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AIRD-02-2R7K | INDUCTOR PWR DRUM CORE 2.7UH |
| AIRD-02-1R5K | INDUCTOR PWR DRUM CORE 1.5UH |
| ECC30DJCB | CONN EDGECARD 60PS .100 PRESSFIT |
| D-SCE-1K-4.8-50-S1-9 | HEAT SHRINK SLEEVE MARKER |
| SPX1431S-L/TR | IC VREF SHUNT PREC ADJ 8-SOICN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DK-DEV-4CGX150N | 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX ((NS |
| DK-DEV-4S100G5N | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For EP4S100G5F RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-4SE530N | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For EP4SE530H35 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-4SGX230N | 功能描述:可編程邏輯 IC 開發(fā)工具 FPGA Development Kit For EP4SGX230KF40C2N RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| DK-DEV-4SGX230N/C2 | 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件狀態(tài):過期 類型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:EP4SGX230KF40C2N 內(nèi)容:板，線纜，電源 標(biāo)準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。