參數(shù)資料
型號(hào): DD28F032SA-150
廠商: INTEL CORP
元件分類: DRAM
英文描述: 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
中文描述: 4M X 8 FLASH 12V PROM, 150 ns, PDSO56
封裝: 14 X 20 MM, 1.20 MM HEIGHT, TSOP-56
文件頁數(shù): 42/49頁
文件大小: 1402K
代理商: DD28F032SA-150
DD28F032SA
E
42
6.10 AC Characteristics for Page Buffer Write Operations
(1)
(Continued)
V
CC
= 5.0V ± 0.5V, 5.0V ± 0.25V, T
A
= 0°C to +70°C
Versions
DD28F032SA-070
DD28F032SA-080
DD28F032SA-100
Symbol
Parameter
Notes
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
t
AVAV
Write Cycle
Time
70
80
100
ns
t
ELWL
CE
X
# Setup to
WE# Going
Low
Address Setup
to WE# Going
Low
Data Setup to
WE# Going
High
0
0
0
ns
t
AVWL
3
0
0
0
ns
t
DVWH
2
50
50
50
ns
t
WLWH
WE# Pulse
Width
40
50
50
ns
t
WHDX
Data Hold from
WE# High
Address Hold
from WE# High
CE
X
# Hold from
WE# High
WE# Pulse
Width High
Read Recovery
before Write
Write Recovery
before Read
2
0
0
0
ns
t
WHAX
2
10
10
10
ns
t
WHEH
10
10
10
ns
t
WHWL
30
30
50
ns
t
GHWL
0
0
0
ns
t
WHGL
60
65
80
ns
NOTES:
For 28F016SA No. 1: CE
X
# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
For 28F016SA No. 2: CE
X
# is defined as the latter of CE
0
# or CE
2
# going low or the first of CE
0
# or CE
2
# going high.
1. These are WE#-controlled write timings, equivalent CE
X
#-controlled write timings apply.
2. Sampled, not 100% tested.
3. Address must be valid during the entire WE# low pulse or the entire CE
X
# low pulse (for CE
X
#-controlled write timings).
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