參數(shù)資料
型號: DD28F032SA-150
廠商: INTEL CORP
元件分類: DRAM
英文描述: 32-MBIT (2 MBIT X 16, 4 MBIT X 8) FlashFile⑩ MEMORY
中文描述: 4M X 8 FLASH 12V PROM, 150 ns, PDSO56
封裝: 14 X 20 MM, 1.20 MM HEIGHT, TSOP-56
文件頁數(shù): 39/49頁
文件大?。?/td> 1402K
代理商: DD28F032SA-150
E
6.9 AC Characteristics for CE
X
#
—Controlled Command Write Operations
(1)
(Continued)
V
CC
= 5.0V ± 0.5V, 5.0V ± 0.25V, T
A
= 0°C to +70°C
DD28F032SA
39
Versions
V
CC
± 5%
DD28F032SA-070
Unit
V
CC
± 10%
DD28F032SA-080
DD28F032SA-100
Sym
Parameter
RP# High
Recovery to
CE
X
#
Going Low
Write
Recovery
before Read
V
PP
Hold from
Valid Status
Register
(CSR, GSR,
BSR) Data at
RY/BY# High
Duration of
Word/Byte
Program
Operation
Duration of
Block Erase
Operation
Notes
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
t
PHEL
1
1
1
μs
t
EHGL
60
65
80
ns
t
QVVL
0
0
0
μs
t
EHQV
1
4,5
4.5
6
Note
7
4.5
6
Note
7
4.5
6
Note
7
μs
t
EHQV
2
4
0.3
10
0.3
10
0.3
10
sec
NOTES:
For 28F016SA No. 1: CE
X
# is defined as the latter of CE
0
# or CE
1
# going low or the first of CE
0
# or CE
1
# going high.
For 28F016SA No. 2: CE
X
# is defined as the latter of CE
0
# or CE
2
# going low or the first of CE
0
# or CE
2
# going high.
1. Read timings during data program and block erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Data program/block erase durations are measured to valid Status Register data.
5. Word/byte program operations are typically performed with 1 programming pulse.
6. Address and data are latched on the rising edge of CE
X
# for all command write operations.
7.
This information will be available in a technical paper. Please call Intel’s Applications Hotline or your local sales office for
more information.
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