參數(shù)資料
型號(hào): DC1011A-B
廠商: Linear Technology
文件頁數(shù): 28/32頁
文件大小: 0K
描述: BOARD DELTA SIGMA ADC LTC2496
軟件下載: QuikEval System
設(shè)計(jì)資源: DC1011A Schematic
DC1011A Design Files
標(biāo)準(zhǔn)包裝: 1
系列: Easy Drive™, QuikEval™
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 6.9
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
已用 IC / 零件: LTC2496
已供物品:
相關(guān)產(chǎn)品: LTC2496CUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496CUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496
2496fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN, VIN(CM) = (IN+ – IN)/2, where IN+ and INare the
selected input channels
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless other wise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: fEOSC = 256kHz ±2% (external oscillator).
Note 8: fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz (internal oscillator) or fEOSC = 280kHz
±2% (external oscillator).
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
DigiTal inpuTs anD DigiTal ouTpuTs
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t1
CS
↓ to SDO Low
l
0
200
ns
t2
CS
↑ to SDO High Z
l
0
200
ns
t3
CS
↓ to SCK↓
Internal SCK Mode
l
0
200
ns
t4
CS
↓ to SCK↑
External SCK Mode
l
50
ns
tKQMAX
SCK
↓ to SDO Valid
l
200
ns
tKQMIN
SDO Hold After SCK
(Note 5)
l
15
ns
t5
SCK Set-Up Before CS
l
50
ns
t6
SCK Hold After CS
l
50
ns
t7
SDI Setup Before SCK
(Note 5)
l
100
ns
t8
SDI Hold After SCK
(Note 5)
l
100
ns
Note 10: The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is fESCK. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses its internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 16: Refer to Applications Information section for performance vs
data rate graphs.
Note 17: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output.
Note 18: For VCC < 3V, VIH is 2.5V for pin fO.
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