VCC f
參數(shù)資料
型號(hào): DC1011A-B
廠商: Linear Technology
文件頁數(shù): 11/32頁
文件大?。?/td> 0K
描述: BOARD DELTA SIGMA ADC LTC2496
軟件下載: QuikEval System
設(shè)計(jì)資源: DC1011A Schematic
DC1011A Design Files
標(biāo)準(zhǔn)包裝: 1
系列: Easy Drive™, QuikEval™
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 6.9
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
已用 IC / 零件: LTC2496
已供物品:
相關(guān)產(chǎn)品: LTC2496CUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496CUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496
2496fb
applicaTions inForMaTion
10F
0.1F
2.7V TO 5.5V
VCC
fO
REF+
REF
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2496
3-WIRE
SPI INTERFACE
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2496 F06
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
1
0
EN
SGL
A2
A1
A0
ODD
BIT 0
DON'T CARE
MSB
SIG
“0”
1
2
3
4
5
6
7
8
9
19
20
21
22
23
24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Figure 6. External Serial Clock, 3-Wire Operation (CS = 0)
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversionresultisshiftedoutofthedevicebyanexternally
generated serial clock (SCK) signal, see Figure 6. CS is
permanently tied to ground, simplifying the user interface
or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after VCC exceeds 2V. The level applied to
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
On the falling edge of EOC, the conversion result is load-
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
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