參數(shù)資料
型號: DC1011A-B
廠商: Linear Technology
文件頁數(shù): 21/32頁
文件大小: 0K
描述: BOARD DELTA SIGMA ADC LTC2496
軟件下載: QuikEval System
設計資源: DC1011A Schematic
DC1011A Design Files
標準包裝: 1
系列: Easy Drive™, QuikEval™
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 6.9
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
已用 IC / 零件: LTC2496
已供物品:
相關產(chǎn)品: LTC2496CUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496CUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496
2496fb
OUTPUT DATA RATE (READINGS/SEC)
0
–10
OFFSET
ERROR
(ppm
OF
V
REF
)
–5
5
10
20
10
50
70
2496 F26
0
15
40
90 100
20 30
60
80
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
VIN(CM) = VREF(CM)
VIN = 0V
fO = EXT CLOCK
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION
(BITS)
12
16
18
22
10
50
70
2496 F25
14
20
40
90 100
20 30
60
80
TA = 85°C
TA = 25°C
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION
(BITS)
12
16
18
20
24
10
50
70
2496 F24
14
22
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
TA = 85°C
TA = 25°C
TA = 25°C, 85°C
OUTPUT DATA RATE (READINGS/SEC)
0
–3500
–FS
ERROR
(ppm
OF
V
REF
)
–3000
–2000
–1500
–1000
0
10
50
70
2496 F23
–2500
–500
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
+FS
ERROR
(ppm
OF
V
REF
)
500
1500
2000
2500
3500
10
50
70
2496 F22
1000
3000
40
90 100
20 30
60
80
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 85°C
TA = 25°C
applicaTions inForMaTion
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejectionoflinefrequenciesremainsunchanged,thusfully
differential input signals with a high degree of symmetry
on both the IN+ and INpins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz(amorethan3xincreaseinoutputrate)theeffective-
ness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full-scale errors, and
decreased resolution, see Figures 21 to 28.
Figure 22. +FS Error vs Output Data
Rate and Temperature
Figure 23.–FS Error vs Output Data
Rate and Temperature
Figure 24. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 25. Resolution (INLMAX ≤ 1LSB) vs
Output Data Rate and Temperature
Figure 26. Offset Error vs Output Data
Rate and Reference Voltage
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET
ERROR
(ppm
OF
V
REF
)
10
30
50
0
20
40
20
40
60
80
2496 F21
100
10
0
30
50
70
90
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
TA = 85°C
TA = 25°C
Figure 21. Offset Error vs Output Data
Rate and Temperature
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