參數(shù)資料
型號(hào)： DC1011A-B
廠商： Linear Technology
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2496
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1011A Schematic
DC1011A Design Files
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 6.9
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
已用 IC / 零件： LTC2496
已供物品： 板
相關(guān)產(chǎn)品： LTC2496CUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#TRPBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496CUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496IUHF#PBF-ND - IC ADC 16BIT DELTA SIG 38-QFN
LTC2496
0
2496fb
applicaTions inForMaTion
Figure 7. Internal Serial Clock, Single Cycle Operation
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle, see Figure 7.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be floating or pulled HIGH
before the conclusion of the POR cycle and prior to each
fallingedgeofCS.Aninternalweakpull-upresistorisactive
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC =1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must
be pulled HIGH before the device pulls SCK HIGH. When
the device is using its own internal oscillator (fO is tied
LOW), the first rising edge of SCK occurs 12s (tEOCTEST
= 12s) after the falling edge of CS. If fO is driven by an
external oscillator of frequency fEOSC, then tEOCTEST =
3.6/fEOSC.
If CS remains LOW longer than tEOCTEST, the first rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 24th rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
10F
0.1F
2.7V TO 5.5V
Hi-Z
2496 F07
CS
SCK
(INTERNAL)
SDI
SDO
CONVERSION
SLEEP
DATA INPUT/OUTPUT
CONVERSION
VCC
fO
REF+
REF–
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2496
4-WIRE
SPI INTERFACE
EOC
1
0
EN
SGL
A2
A1
A0
ODD
DON'T CARE
MSB
SIG
“0”
OPTIONAL
10k
VCC
<tEOCTEST
1
2
3
4
5
6
7
8
9
19
20
21
22
23
24
LSB
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
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