參數(shù)資料
型號： DC1010A-C
廠商： Linear Technology
文件頁數(shù)： 8/32頁
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2487
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1010A Design File
DC1010A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 15
數(shù)據(jù)接口： I²C，串行
已用 IC / 零件： LTC2487
已供物品： 板
相關(guān)產(chǎn)品： LTC2487IDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2487CDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2487CDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2487IDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN
LTC2487
16
2487fd
INPUT DATA FORMAT
The serial input word to the LTC2487 is 16 bits long and
is written into the device input register in two 8-bit words.
The rst word (SGL, ODD, A2, A1, A0) is used to select
the input channel. The second word of data (IM, FA, FB,
SPD, GS2, GS1, GS0) is used to select the frequency
rejection, speed mode (1x, 2x), temperature measure-
ment, and gain.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled), and gain = 1.
The rst conversion automatically begins at power-up using
this default conguration. Once the conversion is complete,
up to two words may be written into the device.
The rst three bits of the rst input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.
If the rst three bits are 000 or 100, the following data is ig-
nored (don’t care) and the previously selected input channel
and conguration remain valid for the next conversion.
If the rst three bits shifted into the device are 101, then
the next ve bits select the input channel for the next
conversion cycle (see Table 3).
Figure 3a. Timing Diagram for Reading from the LTC2487
APPLICATIONS INFORMATION
Figure 3b. Timing Diagram for Writing to the LTC2487
DATA INPUT
ACK BY
LTC2487
ACK BY
LTC2487
ACK BY
LTC2487
(OPTIONAL 2ND BYTE)
START BY
MASTER
SGL ODD
W
0
1
SCL
SDA
EN
A2
A1
A0
7
…8
9
2
12345678
9
1
7-BIT ADDRESS
2487 F03b
IM
FA
EN2
FB
SPD GS2 GS1 GS0
SLEEP
19
23
4
5
6
7
8
SLEEP
DATA OUTPUT
ACK BY
LTC2487
ACK BY
MASTER
ALWAYS LOW
START BY
MASTER
NAK BY
MASTER
LSB
R
MSB
SIG
D23
7
…
89
1
2
9
1
2
3
4
5
6
7
8
9
1
7-BIT
ADDRESS
2487 F03a
SCL
SDA
Table 3. Channel Selection
MUX ADDRESS
CHANNEL SELECTION
SGL
ODD/
SIGN
A2
A1
A0
0
1
2
3
COM
*0
0000
IN+
IN–
00001
IN+
IN–
01000
IN–
IN+
01001
IN–
IN+
10000
IN+
IN–
10001
IN+
IN–
11000
IN+
IN–
11001
IN+
IN–
*Default at power up
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