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參數(shù)資料
| 型號(hào)： | DC1010A-C |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 7/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2487 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC1010A Design File DC1010A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 已用 IC / 零件： | LTC2487 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2487IDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN LTC2487CDE#TRPBF-ND - IC ADC 16BIT DELTA SIG 14-DFN LTC2487CDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN LTC2487IDE#PBF-ND - IC ADC 16BIT DELTA SIG 14-DFN |
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LTC2487
15
2487fd
dress matches the hard wired LTC2487’s address (one of
9 pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2487 issues an ACK by pulling the SDA line low.
The LTC2487 has two registers. The output register (24 bits
long) contains the last conversion result. The input register
(16 bits long) sets the input channel, selects the temperature
sensor, rejection mode, gain and speed mode.
DATA OUTPUT FORMAT
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1μA. When the LTC2487 is addressed for a read
operation, it acknowledges (by pulling SDA low) and acts
as a transmitter. The master/receiver can read up to three
bytes from the LTC2487. After a complete read operation
(3 bytes), a new conversion is initiated. The device will
NAK subsequent read operations while a conversion is
being performed.
The data output stream is 24 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The rst bit is
the conversion result sign bit (SIG) (see Tables 1 and 2).
This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN
corresponds to the selected input signal IN+ – IN–). The
second bit is the most signicant bit (MSB) of the result.
The rst two bits (SIG and MSB) can be used to indicate
over and under range conditions (see Table 2). If both bits
are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set low, the input voltage is below –FS.
The function of these bits is summarized in Table 2. The
16 bits following the MSB bit are the conversion result in
binary, two’s complement format. The remaining six bits
are always 0.
As long as the voltage on the selected input channels (IN+
and IN–) remains between –0.3V and VCC + 0.3V (absolute
maximum operating range) a conversion result is gener-
ated for any differential input voltage VIN from –FS = –0.5
VREF/Gain to +FS = 0.5 VREF/Gain. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to +FS. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
Table 2. LTC2487 Status Bits
Input Range
Bit 23
SIG
Bit 22
MSB
VIN ≥ FS
1
0V ≤ VIN < FS
1/0
0
–FS ≤ VIN < 0V
0
1
VIN < –FS
0
APPLICATIONS INFORMATION
Table 1. Output Data Format
Differential Input Voltage
VIN*
Bit 23
SIG
Bit 22
MSB
Bit 21
Bit 20
Bit 19
…
Bit 6
LSB
Bits 5-0
Always 0
VIN* ≥ FS**
1
0
…
0
000000
FS** – 1LSB
1
0
1
…
1
000000
0.5 FS**
1
0
1
0
…
0
000000
0.5 FS** – 1LSB
1
0
1
…
1
000000
0
1/0***
0
…
0
000000
–1LSB
0
1
…
1
000000
–0.5 FS**
0
1
0
…
0
000000
–0.5 FS** – 1LSB
0
1
0
1
…
1
000000
–FS**
0
1
0
…
0
000000
VIN* < –FS**
0
1
…
1
000000
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 VREF/Gain.
***The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
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