參數(shù)資料
型號: DAC1408D650HN
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 14-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating
封裝: DAC1408D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1408D650HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件頁數(shù): 66/98頁
文件大小: 2600K
代理商: DAC1408D650HN
DAC1408D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 26 November 2010
66 of 98
NXP Semiconductors
DAC1408D650
2
, 4
or 8
interpolating DAC with JESD204A
Table 105. ERROR_HANDLING register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
6
NAD_ERR_CORR
Access
R/W
Value
Description
frame assembler (fa)
not-in-table errors passed to fa
nad (nit and disparity) errors passed to fa
K-character error mode
unexpected K-character errors ignored (at fa)
unexpected K-character errors concealment (at
fa)
nad error mode
nad-errors ignored (at fa)
nad-errors concealment (at fa)
conceal mode
conceal 1 period at fa
conceal 2 periods at fa
conceal 3 periods at fa
conceal 4 periods at fa
disparity error detection configuration
default disparity error detection (table mode)
alternative disparity error detection (cnt mode)
0
1
5
KUX_CORR
R/W
0
1
4
NAD_CORR
R/W
0
1
3 to 2
CORR_MODE[1:0]
R/W
00
01
10
11
1
IMPL_ALT
R/W
0
1
0
IGNORE_ERR
R/W
general error mode
no action
ignore disparity/nit-errors at lane-controller
0
1
Table 106. REINIT_CNTRL register (address 1Ch) bit description
Default settings are shown highlighted.
Bit
Symbol
7
REINIT_ILA_LN3
Access
R/W
Value
Description
lane 3, ila-buffer out-of-range check
no action
lane 3 ila-buffer out-of-range_error activates
reinitialization
lane 2, ila-buffer out-of-range check
no action
lane 2 ila-buffer out-of-range_error activates
reinitialization
lane 1, ila-buffer out-of-range check
no action
lane 1 ila-buffer out-of-range_error activates
reinitialization
lane 0, ila-buffer out-of-range check
no action
lane 0 ila-buffer out-of-range_error activates
reinitialization
0
1
6
REINIT_ILA_LN2
R/W
0
1
5
REINIT_ILA_LN1
R/W
0
1
4
REINIT_ILA_LN0
R/W
0
1
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