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參數(shù)資料
| 型號： | CY25000 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 270K |
| 代理商： | CY25000 |
CY25000
Document #: 38-07424 Rev. *B
Page 7 of 10
Informational Graphs
(continued)
Duty Cycle vs. REFCLK
(VDD=3.0V, Temperature=25C, CLOAD = 15pF)
40
42
44
46
48
50
52
54
56
58
60
0
50
100
150
200
REFCLK (MHz)
D
IDD vs. SSCLK
Temperature=25C, VDD=3.3V, CLOAD=15pF
0
10
20
30
40
50
60
70
0
50
100
150
200
250
SSCLK (M Hz)
REFCLK=SSCLK
REFCLK=30MHz
Measured Spread% vs. VDD over Temperature
(Target Spread = 0.5%, Fout=100MHz, C
LOAD
=15pF)
0.40%
0.45%
0.50%
0.55%
0.60%
2.7
3
3.3
3.6
3.9
VDD (V)
S
-40C
25C
85C
Measured Spread% vs. VDD over
Temperature
(Target Spread = 5.0%, Fout=100MHz, C
LOAD
=15pF)
4.00%
4.50%
5.00%
5.50%
6.00%
2.7
3
3.3
3.6
3.9
VDD (V)
S
-40C
25C
85C
SSCLK Attenduation vs. VDD over Temperature
(Measured at 7th Harmonic with Fnom=100MHz and
Spread=0.5%, C
LOAD
=15pF)
-10
-8
-6
-4
-2
0
2.7
3
3.3
3.6
3.9
VDD (V)
A
-40C
25C
85C
SSCLK Attenduation vs. VDD over Temperature
(Measured at 7th Harmonic with Fnom=100MHz and
Spread=5.0%, C
LOAD
=15pF)
-20
-18
-16
-14
-12
-10
2.7
3
3.3
3.6
3.9
VDD (V)
A
-40C
25C
85C
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY25000-SX001A | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY25002SC-4 | 制造商:Cypress Semiconductor 功能描述: |
| CY25002SXC-4 | 制造商:Cypress Semiconductor 功能描述: |
| CY25010 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Spread Awarea?￠, Ten/Eleven Output Zero Delay Buffer |
| CY25010SC-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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