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參數(shù)資料
| 型號： | CY25000 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 270K |
| 代理商： | CY25000 |
CY25000
Document #: 38-07424 Rev. *B
Page 4 of 10
Programming Description
The customers planning to use the CY25000 need to provide
the programming information described as “ENTER DATA” in
Table 1
and should contact local Cypress Sales.
Additional information on the CY25000 can be obtained from
the Cypress web site at www.cypress.com.
Product Functions
Input Frequency (XIN, pin 1 and XOUT
,
pin 8)
The input to the CY25000 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock
signal is 8 to 166 MHz.
C
XIN
and C
XOUT
(pin 1 and pin 8)
The load capacitors at pin 1 (
C
XIN
) and pin 8 (
C
XOUT
) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
The required values of
C
XIN
and
C
XOUT
can be calculated
using the following formula:
C
XIN
= C
XOUT
= 2C
L
- C
P
Where C
L
is the crystal load capacitor as specified by the
crystal manufacturer and C
P
is the parasitic PCB capacitance.
For example, if a fundamental 16-MHz crystal with C
L
of 16 pF
is used and C
P
is 2 pF, C
XIN
and C
XOUT
can be calculated as:
C
XIN
= C
XOUT
= (2 x 16) – 2 = 30 pF.
If using a driven reference, set C
XIN
and
C
XOUT
to the
minimum value 12 pF.
Output Frequency, SSCLK Output (SSCLK, pin 5)
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON digital control input (SSON = LOW, no
modulation). If modulation is stopped, the clock frequency is
the nominal value of the synthesized frequency without
modulation (spread % = 0). The range of synthesized clock is
from 3–200 MHz.
Spread Percentage (SSCLK, pin 5)
The SSCLK frequency can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
SR3
Rising Edge Slew Rate
SSCLK from 100 to 200 MHz; REFCLK
from 100 to 166 MHz 20%–80% of V
DD
SSCLK from 100 to 200 MHz; REFCLK
from 100 to 166 MHz 80%–20% of V
DD
SSCLK = 200 MHz. Spread on
SSCLK = 66 MHz. Spread on
SSCLK = 14.3 MHz. Spread on
REFCLK output only
1.2
1.6
2.0
V/ns
SR4
Falling Edge Slew Rate
1.2
1.6
2.0
V/ns
tj1
Peak Cycle-to-Cycle Jitter.
SSCLK pin
100
150
200
100
200
300
400
200
ps
ps
ps
ps
tj2
Peak Cycle-to-Cycle Jitter,
REFCLK
Power-down Time
(pin3 = PD#)
Output Disable Time
(pin3 = OE)
Output Enable Time
(pin3 = OE)
Power-up Time,
Crystal is used
Power-up Time,
Reference clock is used
t
STP
Time from falling edge on PD# to stopped
outputs (Asynchronous)
Time from falling edge on OE to stopped
outputs (Asynchronous)
Time from rising edge on OE to outputs at
a valid frequency (Asynchronous)
Time from rising edge on PD# to outputs
at valid frequency (Asynchronous)
Time from rising edge on PD# to outputs
at valid frequency (Asynchronous)
150
300
ns
T
OE1
150
300
ns
T
OE2
150
300
ns
t
PU1
3
5
ms
t
PU2
2
3
ms
Table 1.
Pin
Function
Pin Name
Input
Frequency
XIN and XOUT
C
XIN
and
C
XOUT
XIN and
XOUT
1 and 8
pF
ENTER DATA ENTER DATA
Output
Frequency
SSCLK
Spread
Percent
SSCLK
Reference
Output
REFOUT
Power-down or
Output Enable
PD#/OE
Frequency
Modulation
SSCLK
Pin#
Units
1 and 8
MHz
ENTER DATA
5
5
%
6
3
5
MHz
On or Off
ENTER DATA
Select PD# or OE
ENTER DATA
kHz
30
PROGRAM
VALUE
ENTER
DATA
AC Electrical Characteristics
[1]
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
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