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參數(shù)資料
| 型號： | CY25000 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 270K |
| 代理商： | CY25000 |
CY25000
Document #: 38-07424 Rev. *B
Page 5 of 10
Reference Output (REFOUT, pin 6)
The reference clock output has the same frequency and the
same phase as the input clock. This output can be
programmed to be enabled (clock on) or disabled (High-Z,
clock off). If this output is not needed, it is recommended that
users request the disabled (High-Z, Clock Off) option.
Frequency Modulation
The frequency modulation is programmed at 30 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher modulation frequency is required.
Power-down or Output Enable (PD# or OE, pin 3):
Users can select either PD# or OE function which are also
factory programmable.
Application Circuit
[3, 4, 5]
Switching Waveforms
Notes:
3. Since the load capacitors (C
and C
) are provided by the CY25000, no external capacitors are needed on the XIN
and XOUT pins to match the crystal load
capacitor (C
). Only a single 0.1-
μ
F bypass capacitor is required on the V
pin.
4. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).
5. If SSON (pin 7) is LOW (V
SS
), the frequency modulation will be stopped on SSCLK pin (pin 5).
1
2
3
4
VDD
XOUT
VSS
SSCLK
REFCLK
5
6
7
8
XIN
SSON
C
Power
0.1
μ
F
VDD
VDD
PD#/OE
Crystal
Duty Cycle Timing (DC = t
1A
/t
1B
)
t
1A
t
1B
OUTPUT
Output Rise/Fall Time (SSCLK and REFCLK)
OUTPUT
Tr
V
DD
0V
Tf
Output Rise time (Tr) = (0.6 x V
DD
)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x V
)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Power-down Timing and Power-up Timing
V
DD
POWER-
DOWN
0V
CLKOUT
t
PU
t
STP
V
IL
V
IH
(Asynchronous
)
High Impedance
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| CY25000-SX001A | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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| CY25010SC-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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