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參數(shù)資料
| 型號： | CY25000 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 270K |
| 代理商： | CY25000 |
CY25000
Document #: 38-07424 Rev. *B
Page 3 of 10
Absolute Maximum Rating
Supply Voltage (V
DD
)........................................–0.5 to +7.0V
DC Input Voltage......................................–0.5V to V
DD
+ 0.5
Storage Temperature (Non-Condensing)....–55
°
C to +125
°
C
Junction Temperature................................ –40
°
C to +125
°
C
Data Retention @ Tj=125
°
C................................. > 10 Years
Package Power Dissipation......................................350 mW
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
Parameter
Description
Min.
3.13
0
Typ.
3.30
Max.
3.45
70
15
30
Unit
V
°C
pF
MHz
V
DD
T
A
C
LOAD
F
ref
Supply Voltage
Ambient Temperature
Max. Load Capacitance @ pin 5 and pin 6
External Reference Crystal
(Fundamental tuned crystals only)
External Reference Clock
SSCLK output frequency, C
LOAD
= 15 pF
REFCLK output frequency, C
LOAD
= 15 pF
Power-up time for all VDDs to reach minimum
specified voltage (power ramps must be monotonic)
8
8
3
8
166
200
166
500
MHz
MHz
MHz
ms
F
SSCLK
F
REFCLK
t
PU
0.05
DC Electrical Characteristics
Parameter
I
OH
I
OL
V
IH
V
IL
I
IH
Description
Condition
Min.
10
10
0.7V
DD
Typ.
14
14
Max.
Unit
mA
mA
V
V
μ
A
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Input High Current, PD#/OE
and SSON pins
Input Low Current, PD#/OE
and SSON pins
Output Leakage Current
Programmable Capacitance
at pin 1 and pin 8
V
OH
= V
DD
– 0.5, V
DD
= 3.3V (source)
V
OL
= 0.5, V
DD
= 3.3V (sink)
CMOS levels, 70% of V
DD
CMOS levels, 30% of V
DD
V
in
= V
DD
0.3V
DD
10
I
IL
V
in
= V
SS
10
μ
A
I
OZ
C
XIN
/C
XOUT[1, 2]
Three-state output, PD#/OE = 0
Capacitance at minimum setting
Capacitance at maximum setting
Input pins excluding XIN and XOUT
–10
10
μ
A
pF
pF
pF
12
60
5
C
IN[1]
Input Capacitance at pin 3
and pin 7
Supply Current
7
I
VDD
V
DD
= 3.45V, Fin = 30 MHz,
REFCLK = 30 MHz, SSCLK = 66 MHz,
C
LOAD
= 15 pF, PD#/OE = SSON = V
DD
V
DD
= 3.45V, Device powered down with
PD#/OE = 0V
25
35
mA
I
DDS
Stand by current
15
30
μ
A
AC Electrical Characteristics
[1]
Parameter
DC
Description
Condition
Min.
45
40
Typ.
50
50
Max.
55
60
Unit
%
%
Output Duty Cycle
Output Duty Cycle
SSCLK, Measured at V
DD
/2
REFCLK, Measured at V
DD
/2
Duty Cycle of CLKIN = 50%.
SSCLK from 3 to 100 MHz; REFCLK from
10 to 100 MHz. 20%–80% of V
DD
SSCLK from 3 to 100 MHz; REFCLK from
10 to 100 MHz. 80%–20% of V
DD
SR1
Rising Edge Slew Rate
0.7
1.1
1.5
V/ns
SR2
Falling Edge Slew Rate
0.7
1.1
1.5
V/ns
Notes:
1. Guaranteed by characterization, not 100% tested.
2. Contact factory for desired crystal load programming.
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