參數(shù)資料
型號(hào): CS5534-ASZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 20/43頁(yè)
文件大小: 0K
描述: IC ADC 24BIT 4CH W/LNA 24-SSOP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
采樣率(每秒): 3.84k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 45mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)差分,單極;4 個(gè)差分,雙極
配用: 598-1016-ND - EVAL BOARD FOR CS5534
CS5531/32/33/34-AS
DS289F5
27
Filter Rate Select, FRS[19]
0
Use the default output word rates.
1
Scale all output word rates and their corresponding filter characteristics by a factor of 5/6.
NU (Not Used)[18:0]
0
Must always be logic 0. Reserved for future upgrades.
2.4. Setting up the CSRs for a Measurement
The CS5531/32/33/34 have four channel-setup reg-
isters (CSRs). Each CSR contains two 16-bit Setups
which are programmed by the user to contain data
conversion information such as: 1) which physical
channel will be converted, 2) at what gain will the
channel be converted, 3) at what word rate will the
channel be converted, 4) will the output conversion
be unipolar or bipolar, 5) what will be the state of the
output latch during the conversion, 6) will the con-
verter delay the start of a conversion to allow time
for the output latch to settle before the conversion is
begun, and 7) will the open circuit detect current
source be activated for that Setup. In addition, when
the OGS bit in the Configuration Register is set, the
Setup selects which set of offset and gain registers to
use when performing conversions or calibrations.
Note that a particular physical input channel can be
represented in more than one Setup with different
output rates, gain ranges, etc. (i.e. each Setup is in-
dependently defined). Refer to section 2.4.1 for
more details about the Channel Setup Registers.
Each 32-bit CSR is individually accessible and
contains two 16-bit Setups. As an example, to con-
figure Setup 1 in the CS5531/32/33/34 with the
write individual channel-setup register command
(0x05 hexadecimal), bits 31 to 16 of CSR 1 con-
tains the information for Setup 1 and bits 15 to 0
contain the information for Setup 2. Note that while
reading/writing CSRs, two Setups are accessed in
pairs as a single 32-bit CSR register. Even if one of
the Setups isn’t used, it must be written to or read.
Examples detailing the power of the CSRs are pro-
vided in section 2.6.3.
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CS5534-BSZ/H 制造商:Cirrus Logic 功能描述:
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