參數(shù)資料
型號: CS5364-CQZR
廠商: Cirrus Logic Inc
文件頁數(shù): 28/42頁
文件大?。?/td> 0K
描述: IC ADC 4CH 114DB 216KHZ 48-LQFP
標準包裝: 2,000
位數(shù): 24
采樣率(每秒): 216k
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 1
功率耗散(最大): 580mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個差分,單極
配用: CDB5364-ND - EVALUATION BOARD FOR CS5364
34
DS625F4
CS5364
5.6
04h (HPF) High-Pass Filter Register
Default: 0x00, all high-pass filters enabled.
The High-Pass Filter Register is used to enable or disable a high-pass filter that exists for each channel.
These filters are used to perform DC offset calibration, a procedure that is detailed in “DC Offset Control”
5.7
05h Reserved
5.8
06h (PDN) Power Down Register
Default: 0x00 - everything powered up
The Power Down Register is used as needed to reduce the chip’s power consumption.
Bit[7] RESERVED
Bit[6] RESERVED
Bit[5] PDN-BG When set, this bit powers-down the bandgap reference.
Bit[4] PDN-OSC controls power to the internal oscillator core. When asserted, the internal oscillator core is
shut down, and no clock is supplied to the chip. If the chip is running off an externally supplied clock at the
MCLK pin, it is also prevented from clocking the device internally.
Bit[1:0] PDN When any bit is set, all clocks going to a channel pair are turned off, and the serial data outputs
are forced to all zeroes.
5.9
07h Reserved
5.10
08h (MUTE) Mute Control Register
Default: 0x00, no channels are muted.
The Mute Control Register is used to mute or unmute the serial audio data output of individual channels.
When a bit is set, that channel’s serial data is muted by forcing the output to all zeroes.
R/W
765
43
210
R/W
RESERVED RESERVED RESERVED RESERVED
HPF4
HPF3
HPF2
HPF1
R/W
765
43
210
RESERVED
-
R/W
765
43
210
R/W
RESERVED
PDN-BG
PDN-OSC
RESERVED RESERVED
PDN43
PDN21
R/W
765
43
210
RESERVED
-
R/W
765
43
210
R/W
RESERVED RESERVED RESERVED RESERVED
MUTE4
MUTE3
MUTE2
MUTE1
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